Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2005-03-01
2005-03-01
McLean-Mayo, Kimberly (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S106000, C711S003000, C710S036000, C710S044000, C710S052000
Reexamination Certificate
active
06862673
ABSTRACT:
A mechanism for maintaining the first-in first-out order of commands in a multiple-input and multiple-output buffer structure includes a command number generator for generating and assigning a command number to each command entering the buffer structure, and a command number comparator for comparing the command number of the outgoing command at each buffer in the buffer structure to determine which command should exit. Both command number generator and command comparator have a cyclic counter that has a period greater than or equal to the total number of allowable buffer entries in the buffer structure. For maintaining order of posted and non-posted command queues, a pending posted write counter is used in the posted command queue to record the number of pending posted write command and each entry in the non-posted command queue is associated with a dependency counter.
REFERENCES:
patent: 6481251 (2002-11-01), Meier et al.
patent: 6671747 (2003-12-01), Benkual et al.
Chen Tsan-Hui
Lee Shao-Kuang
Su Jen-Pin
McLean-Mayo Kimberly
Silicon Integrated Systems Corporation
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