Command issuing apparatus for high-speed serial interface

Details Command issuing apparatus for high-speed serial interface Command issuing apparatus for high-speed serial interface

2006-10-24

2006-10-24

Nguyen, Tanh Q. (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output command process

C710S006000, C710S007000, C710S020000, C710S029000, C710S036000, C710S039000, C710S052000, C718S001000, C718S100000, C718S101000, C718S102000, C711S100000, C711S154000, C712S214000, C712S215000, C712S220000, C712S245000

Reexamination Certificate

active

07127530

ABSTRACT:
In order to reduce load placed on a CPU (central processing unit) in providing SBP-2 (serial bus protocol 2) initiator capability, provided are a sequence control circuit activated by the CPU for controlling a command issue sequence, a packet processing circuit for assembling operation request blocks (ORB) into a transmission packet and extracting a status from a received packet; buffer for storing a command ORB provided by the CPU; a buffer for storing a management ORB provided by the CPU; a buffer for storing a status received for an issued management ORB and providing the status to the CPU; and a buffer for command for storing a status received for an issued command ORB and providing the status to the CPU.

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