Combo memory cell

Details Combo memory cell Combo memory cell

2007-07-02

2009-06-16

Luu, Pho M. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Semiconductive

C365S189050, C365S205000, C365S185170, C365S049110

Reexamination Certificate

active

07548456

ABSTRACT:
A combo memory cell having a SRAM cell and a mask-ROM code programmer. The SRAM cell comprises first and second inverters. The first inverter comprises a first PMOS transistor and a first NMOS transistor. Gates of the first PMOS and NMOS transistors are commonly connected to a first input node and drains thereof commonly connected to a first output node. The second inverter comprises a second PMOS transistor and a second NMOS transistor. Gates of the second PMOS and NMOS transistors are commonly connected to a second input node and drains thereof commonly connected to a second output node. The first input node and the second output node are connected, as are the second input node and the first output node. The mask-ROM code programmer is coupled to the sources of the first and second PMOS transistors or the first and second NMOS transistors.

REFERENCES:
patent: 5923582 (1999-07-01), Voss
patent: 7023744 (2006-04-01), Shimanek et al.
patent: 2006/0198204 (2006-09-01), Lambrache et al.

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