Combining the address-mapping and page-referencing steps in...

Details Combining the address-mapping and page-referencing steps in... Combining the address-mapping and page-referencing steps in...

2006-06-19

2008-10-14

Lane, Jack A (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S105000, C365S230030, C365S238500

Reexamination Certificate

active

07437501

ABSTRACT:
A method and apparatus for parallelizing address-mapping and page referencing in a memory controller. The page referencing may apply an input address to two separate content addressable memory components along with masks from a configuration register identifying rank-bank bits, page status bits and non-column bits. The content addressable memories each determine if matching content is present generating a ‘hit’ or ‘miss.’ The hit and miss indicators are applied to combinational logic to determine whether to generate a CAS, RAS-CAS or PRE-RAS-CAS indicator.

REFERENCES:
patent: 6535966 (2003-03-01), Cherabuddi et al.
patent: 2002/0065981 (2002-05-01), Jenne et al.
patent: 2005/0204094 (2005-09-01), Rotithor et al.

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