Combining plural data lines and clock lines into set of parallel

Details Combining plural data lines and clock lines into set of parallel Combining plural data lines and clock lines into set of parallel

1997-09-04

2000-02-01

Barry, Lance Leonard

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

G06F 1300

Patent

active

060214503

ABSTRACT:
A data transfer system includes a plurality of functional blocks each provided with a function module for controlling data transfer between memories of the plurality of functional blocks, by being connected to a function module of other functional blocks via n sets of data signal lines and clock signal lines so that the data transfer proceeds in a synchronized manner. Each of the n sets of data signal lines and clock signal lines is appropriately combined with one another depending on a required condition for communicating with destination functional blocks, such that a plurality of sets of data signal lines and clock signal lines are used for parallel transfer and a single set of a data signal line and a clock signal line is used for serial transfer.

REFERENCES:
patent: 5590284 (1996-12-01), Crosetto
patent: 5596724 (1997-01-01), Mullins et al.

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