Combined turbo-code/convolutional code decoder, in...

Details Combined turbo-code/convolutional code decoder, in... Combined turbo-code/convolutional code decoder, in...

2007-03-13

2007-03-13

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

Reexamination Certificate

active

10653721

ABSTRACT:
A combined decoder reuses input/output RAM of a turbo-code decoding circuit as alpha-RAM or beta-RAM for a convolutional code decoding circuit. Additional operational units are used for both turbo-coding and convolutional coding. An effective harware folding scheme permits calculation of 256 states serially on 8 ACS units.

REFERENCES:
patent: 6226773 (2001-05-01), Sadjadpour
patent: 6484283 (2002-11-01), Stephen et al.
patent: 6829313 (2004-12-01), Xu
patent: 2001/0044919 (2001-11-01), Edmonston et al.
patent: 2002/0061069 (2002-05-01), Tran et al.
patent: 2002/0119803 (2002-08-01), Bitterlich et al.
patent: 2003/0018942 (2003-01-01), Seo
patent: 2003/0097633 (2003-05-01), Nguyen
patent: 2003/0208716 (2003-11-01), Wolf
patent: 2001285079 (2001-10-01), None
Page 473 from Blahut, Richard. Theory and pratice of error control codes. Published 1983 by Addison-Wesley Publishing company.

Affiliated with

Also associated with

Rating

Combined turbo-code/convolutional code decoder, in... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Combined turbo-code/convolutional code decoder, in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Combined turbo-code/convolutional code decoder, in... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3793751