Combined single error correction/device kill detection code

Details Combined single error correction/device kill detection code Combined single error correction/device kill detection code

2007-06-05

2011-11-08

Abraham, Esaw (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S784000, C714S785000

Reexamination Certificate

active

08055975

ABSTRACT:
In one embodiment, an apparatus includes a check/correct circuit coupled to a control circuit. The check/correct circuit is coupled to receive a block of data and corresponding check bits. The block of data is received as N transmissions, each transmission including M data bits and L check bits. The check/correct circuit is configured to detect one or more errors in each of a plurality of non-overlapping windows of K bits in the M data bits, responsive to the M data bits and the L check bits. The control circuit is configured to record which of the plurality of windows have had errors detected and, if a given window of the plurality of windows has had errors detected in each of the N transmissions of the block, the control circuit is configured to signal a device failure. Each of K, L, M, and N are integers greater than one.

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Mark Hayter, “Zen and the Art of SOC Design,” Microprocessor Summit 2006, Session MPS-960 High End Processors, P.A. Semi, Inc., 14 pages.
James B. Keller, “The PWRficient Processor Family,” PA Semi, Oct. 2005, 31 pages.

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