Combined response cancellation for load command

Details Combined response cancellation for load command Combined response cancellation for load command

2007-10-31

2010-10-19

Lane, Jack A (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S119000, C711S146000, C709S213000, C709S214000, C709S216000

Reexamination Certificate

active

07818509

ABSTRACT:
A cache coherency technique used in a multi-node symmetric multi-processor system that reduces the number of message phases of a read request from 5 to 4, canceling the combined response phase for read requests in most cases, thereby improving system performance and reducing the overall system power consumption.

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patent: 2008/0181161 (2008-07-01), Gi Kim et al.

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