Combined processing and non-volatile memory unit array

Details Combined processing and non-volatile memory unit array Combined processing and non-volatile memory unit array

2011-06-21

2011-06-21

Le, Don P (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S041000

Reexamination Certificate

active

07965101

ABSTRACT:
A reconfigurable logic device comprises an array of tiles interconnected through a routing network, each tile comprises both a processing unit including volatile configuration memory and a Random Access Memory unit.

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European Search Report issued in European Patent Application No. 09153966.8-1243, mailed Aug. 5, 2009.
Asari, K., et al., “FeRAM Circuit Technology for System on a Chip”, Proceedings of the First NASA/DOD Workshop on Evolvable Hardware, Jul. 1999, pp. 193-197, Los Alamitos CA USA.

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