Combined multiplex or/flop

Electronic digital logic circuitry – Multifunctional or programmable – Sequential or with flip-flop

Reexamination Certificate

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Details

C326S113000

Reexamination Certificate

active

11304165

ABSTRACT:
In one embodiment, a combined mux/storage circuit comprises a latch element, a plurality of passgates connected to the latch element, and logic circuitry. Each passgate has an input coupled to receive a signal representing a respective mux input and is configured to open and close responsive to respective pairs of control signals. The logic circuitry is coupled to receive a clock signal, a delayed clock signal, and mux select control signals, and is configured to generate pulses on the pair of control signals to control a passgate that has an input coupled to receive the signal representing a selected mux inputs, as indicated by the mux select control signals. The width of the pulses is dependent on the clock signal and the delayed clock signal. The latch element is configured to latch the signal representing the selected mux input in parallel with the selected mux input being driven as an output of the mux/storage circuit.

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patent: 5426380 (1995-06-01), Rogers
patent: 6629276 (2003-09-01), Hoffman et al.
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U.S. Appl. No. 11/304,854, filed Dec. 15, 2005, 26 pages.
U.S. Appl. No. 11/304,855, filed Dec. 15, 2005, 26 pages.
Samuel D. Naffziger, et al., “The Implementation of the Itanium 2 Microprocessor,” IEEE Journal of Solid-State Circuits, vol. 37, No. 11, Nov. 2002, 13 pages.

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