Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
Reexamination Certificate
1998-12-30
2002-02-05
Nguyen, Hiep T. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Memory configuring
C711S153000, C703S024000
Reexamination Certificate
active
06345349
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the memory arrangement of computing devices. In particular, the present invention relates to the use of a single high speed mass storage memory as a unitary memory in a computing device.
2. Description of the Related Art
FIG. 1
illustrates the general configuration of the typical memory arrangement in a personal computer. As shown, a central processing unit (CPU) works with two types of memories. The main memory, usually implemented as volatile dynamic random access memory (DRAM), stores data used by the CPU during processing. A separate mass storage memory, typically a hard drive with a rotating media disk, is also provided to store large amounts of data which are expected to be accessed only infrequently by the CPU. Because there are two different types of memories, there are also separate memory controls, etc., for controlling the different memories, such as DRAM control for the DRAM main memory and a disk drive interface unit for the disk drive.
Such a memory architecture increases complexity and cost. Separate chips are typically used for the different interfaces, thus increasing the number of pins and physical space required for memory. The presence of both types of memory tends to impart the computing device with the disadvantages of each. The storage of large amounts of data in a relatively slow mass storage device obviously degrades performance. But, in addition, DRAM typically requires a large amount of power consumption, which increases roughly in proportion with the size of the memory. The volatile nature of the DRAM memory also means that time is needed for boot-up after the computing device is turned on, thus making the device unavailable for immediate use.
Radically different storage techniques have recently been proposed and described as improving the performance of mass storage devices. These include a variety of probe based storage devices and electron beam storage devices (see, for example, U.S. Pat. Nos. 5,446,687, 5,546,337 and 5,604,706 assigned to Terastore, Inc.). The access time of fifty microseconds for these devices is about {fraction (1/200)}th of the access time offered by present disk drives.
Another category of recently developed devices, referred to as optical polymer or polymer memory, may have access times as low as one microsecond, which is {fraction (1/2000)}th to {fraction (1/10000)}th that of presently available disk drives. These devices have been described in, for example, patent documents WO 09733275 and WO 09724715, assigned to Opticom ASA.
Despite the development of these new types of mass storage memories, computing devices typically employ a standardized operating system (OS) to control the transfer of data between a central processing unit and connected memories. The operating system was developed with the assumption that the device would have the memory arrangement shown in FIG.
1
and contains instructions for controlling the transfer of data between main memory and a disk drive serving as mass storage memory. Therefore, even though there may be advances in mass storage memories, the overall performance of the devices will not increase commensurately because their operating systems operate on the assumption that there will be a memory arrangement as shown in FIG.
1
.
SUMMARY OF THE INVENTION
The present invention is directed to a method of utilizing a high speed mass storage device in a low-cost computing device. In a first aspect of the invention, a memory device includes a mass storage memory configured into a main memory portion and a mass storage portion; and a memory access unit, the memory access unit storing the configuration data marking the partition between the main memory portion and the mass storage portion of the mass storage device and controlling the transfer of data to and from the mass storage memory according to whether the data is located in the main memory portion or the mass storage portion.
REFERENCES:
patent: 5317718 (1994-05-01), Jouppi
patent: 5535357 (1996-07-01), Moran et al.
patent: 5924113 (1999-07-01), Estakhri et al.
patent: 5966727 (1999-10-01), Nishino
patent: 6065077 (2000-05-01), Fu
Antonelli Terry Stout & Kraus LLP
Nguyen Hiep T.
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