Combined logic and memory circuit with built-in memory test

Details Combined logic and memory circuit with built-in memory test Combined logic and memory circuit with built-in memory test

1996-08-14

1999-12-07

Nguyen, Hoa T.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

714 42, G11C 2900

Patent

active

060000481

ABSTRACT:
A built-in self test (BIST) for an integrated circuit (IC) including a large logic section, a large dynamic random access memory (DRAM), and a smaller static RAM (SRAM). Additional logic circuitry is included within the IC to enable the IC to test the DRAM, that is, a built-in self test of the DRAM. The DRAM test program is stored in the SRAM by the VLSI tester, and portions of the existing logic circuitry may be used for the memory testing. The VLSI tester initiates the DRAM test and inspects the results of the test but does immediately participate in the DRAM testing. Thereby, a VLSI tester can test both the logic and DRAM portions of the IC, eliminating the need for separate memory test equipment.

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Alpine VGA Family--CL-GD543X: Technical Reference Manual, 3rd ed., 1994, Cirrus Logic, Inc. Fremont, CA pp.3-i-3-35.

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