Combined leading one and leading zero anticipator

Details Combined leading one and leading zero anticipator Combined leading one and leading zero anticipator

1996-11-18

1999-11-30

Ngo, Chuong Dinh

Boots, shoes, and leggings

G06F 738

Patent

active

059930519

ABSTRACT:
A floating point unit (FPU) is described which processes normalized binary numbers. All multiply, add, and subtract calculations are performed using the format (A*B)+C or (A*B)-C. The operation A*B is performed in parallel with the alignment of C to the product of A*B. An output of the multiplier and the aligned operand C are applied to a carry save adder, whose output is then applied to a carry propagate adder to generate the result A*B.+-.C. The output of the carry save adder is also applied to a combined leading one anticipator (LOA) and leading zero anticipator (LZA). The output of the carry propogate adder is provided to a post normalizer. The output of the combined LOA/LZA is applied to the input of a multiplexer, with the control input of the multiplexer being connected to the most significant bit of the adder output, where this most significant bit indicates whether the result is positive or negative. The output of the multiplexer will thus reflect the leading zero count, if the output of the adder is a positive number, or the leading one count, if the output of the adder is a negative number. The resulting count is then used to normalize the result of A*B.+-.C.

REFERENCES:
patent: 4841467 (1989-06-01), Ho et al.
patent: 5550767 (1996-08-01), Taborn et al.
Erdem Hokenek et al., "Second-Generation RISC Floating Point With Multiply-Add Fused," IEEE Journal of Solid-State Circuits, vol. 25, No. 5, Oct. 1990, pp. 1207-1212.

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