Combined in-situ high density plasma enhanced chemical vapor dep

Details Combined in-situ high density plasma enhanced chemical vapor dep Combined in-situ high density plasma enhanced chemical vapor dep

1999-02-12

1999-10-19

Chaudhuri, Olik

Active solid-state devices (e.g., transistors, solid-state diode

With means to control surface effects

Insulating coating

438641, 438758, 438760, H01L 2128

Patent

active

059694092

ABSTRACT:
A wafer planarization process which utilizes combined high density plasma chemical vapor deposition (HDP-CVD) process and chemical mechanical polishing (CMP) process is disclosed. This process includes the steps of (a) forming a first HDP-CVD layer on the surface of a semiconductor wafer using a first HDP-CVD composition having a higher etching/depositing component ratio and thus a lower CMP removal rate; (b) forming a second HDP-CVD layer on the first HDP-CVD layer using the same HDP-CVD process but with a second HDP-CVD composition having a highest etching/depositing component ratio and thus the lowest CMP removal rate; (c) forming a third HDP-CVD layer on the second HDP-CVD layer using the same HDP-CVD process but with a third HDP-CVD composition having a low etching/depositing component ratio and thus a high CMP removal rate; and (d) using a chemical mechanical process to remove at least a part of the third HDP-CVD layer using the second HDP-CVD layer as a stopper. All the three HDP-CVD compositions contain the same etching and silicon-containing deposition components so as to improve the CMP efficiency without incurring substantially increased fabrication cost.

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