Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1999-05-07
2002-07-02
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S113000, C714S006130, C714S805000, C710S022000
Reexamination Certificate
active
06415355
ABSTRACT:
BACKGROUND OF THE INVENTION
This application is based on Japanese Patent Application No. 10-127439, filed May 11, 1998, and Japanese Patent Application No. 10-281249, filed Oct. 2, 1998, the contents of which are incorporated herein by reference.
The present invention relates to a disk array apparatus having a plurality of disk drives and, more particularly, to a disk array controller which comprises a cache memory for temporarily storing transfer data between a disk drive and host apparatus, and controls access to the disk drives, and a cache control method applied to the controller.
A disk array apparatus is known as an external storage device, which comprises a plurality of disk drives, achieves high-speed access by parallelly driving the plurality of disk drives, and improves reliability by a redundant arrangement.
A disk array apparatus of this type generates parity data as data correction information for write data transferred from a host apparatus, and writes that data in one of the plurality of disk drives. Hence, even when a failure has occurred in one of the plurality of disk drives, data in the failed disk drive can be restored using the stored parity data and data in the remaining disk drives.
As one data redundancy scheme using parity or the like, RAID (Redundant Arrays of Inexpensive Disks) is known. RAID has various levels depending on the arrangements of disk array apparatuses; levels 3 and 5 are prevalent. RAID of level 3 is called RAID3, and is suitable for sequential access (or jobs that require such access) for large data transfers. On the other hand, RAID of level 5 is called RAID5, and is suitable for random access (or jobs that require such access), i.e., frequent read/write access of small data.
The disk array apparatus normally has a cache memory (disk cache) for temporarily storing transfer data between the disk drive and host apparatus. In such arrangement, when target data is present in the cache memory, the target data can be accessed at high speed from the cache memory without accessing the disk drives (i.e., without mechanically accessing them) irrespective of the RAID levels (RAID3, RAID5, and the like).
In RAID3, update parity is generated by segmenting update data transferred from the host apparatus. By contrast, in RAID5, update parity is generated using update data transferred from the host apparatus, data before update, which is stored in a given area of the disk drive where the update data is to be stored, and parity before update (parity data) stored in a given area of another disk drive corresponding to the storage location of the update data.
In a conventional disk array controller, generating update parity for update data transferred from the host apparatus must be implemented by a firmware program in the controller or the controller itself must be configured as a dedicated hardware apparatus. However, implementation by firmware suffers a problem of limited processing speed, and that by dedicated hardware suffers a problem of a complicated circuit.
Hence, the present applicant has proposed a disk array controller, which can attain a simple arrangement, high-speed processing, and easy control by providing a function of generating parity data using read/write data upon cache memory access to the disk cache means side having a cache memory, in Japanese Patent Application No. 8-234264.
In this disk cache controller, data is distributed and stored on the cache memory premised on RAID3, and a control circuit for the cache memory (cache control means) reads out data from the cache memory and EX-ORs the readout data, thus efficiently generating parity data.
However, when this scheme is applied to RAID5, data and parities before update are widely dispersed in the cache memory, and the cache memory area cannot be efficiently used. The reason for this will be explained below.
In RAID3, since update parity is generated based only on update data upon updating data, all data on the cache memory match those on a disk array (disk drive). For this reason, even when the update data is left on the cache memory, it can be used as read data.
By contrast, in RAID5, data and parity before update must be read out, and EX-ORed with update data upon updating data. For this reason, when the update data, and data and parity before update are allocated on the cache memory by the same. method as in RAID3 that generates update parity based only on update data, only the area (⅓ area) of update data on the cache memory is used as that of cache data (read data) (i.e., the area where a copy of data in the disk drive is stored), and the areas of data and parity before update (⅔ area of the cache memory) are wasted.
In this manner, when the same cache control scheme as that for RAID3 is applied to RAID5, data and parities before update, which cannot be used as cache data, are randomly present on the cache memory, and the limited area of the cache memory cannot be efficiently used.
BRIEF SUMMARY OF THE INVENTION
The present invention has been made in consideration of the above situation, and has as its object to provide a disk array controller, which can efficiently generate update parity on the basis of update data, and data and parity before update using a cache memory upon updating data, and can reduce any wasteful area on the cache memory, which cannot be used as cache data, and a cache control method applied to the controller.
It is another object of the present invention to provide a disk array controller, which can efficiently restore original data on the basis of data in the remaining normal disk drives and parity data using a function of generating update parity from update data, and data and parity before update, when a failure has occurred in one of a plurality of disk drives that form a disk array, and a cache control method applied to the controller.
It is still another object of the present invention to provide a disk array controller which can efficiently restore data without being influenced by the number of disk drives (the number of elements) that form a disk array, and a cache control method applied to the controller.
According to the present invention, a disk array controller which comprises external input/output means for controlling input/output with an external host apparatus, disk drive input/output means which allows connection to a disk drive group including N disk drives which form a disk array for storing data input from the host apparatus, disk cache means having a cache memory which temporarily stores transfer data between the disk drives and host apparatus and is managed in units of blocks, and main control means for controlling the respective means, is characterized in that in order to allow generation of parity data on the basis of data before update and parity data before update corresponding to update data upon transferring the update data from the host apparatus, in addition to a first area in which the update data is written, a second area, in which data before update and parity data before update read from one of the N disk drives are temporarily written with a predetermined positional relationship under the control of the main control means, is assured on the cache memory within a predetermined address range, and the disk cache means comprises an EX-OR circuit for EX-ORing two data bit by bit, and cache control means for, when a specific cache access command appended with a request address which indicates a storage location of the update data in the cache memory is supplied from the main control means or disk drive input/output means upon generating parity data in correspondence with the update data transferred from the host apparatus, sequentially reading out the update data at the storage location in the cache memory, which is indicated by the request address, and data before update and parity data before update at storage locations in the second area, which correspond to the storage location of the update data, and making the EX-OR circuit EX-OR the readout data, so as to generate parity data as an EX-OR of the updat
Bataille Pierre-Michel
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Kim Matthew
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