Combinational logic circuit, its design method and integrated ci

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

716 5, 716 6, G06F 1750

Patent

active

061675547

ABSTRACT:
A combinational logic circuit having at least one primary input terminal and at least one primary output terminal comprises a plurality of VDDH gates having an input node and an output node and operated by a standard operating voltage and a plurality of VDDL gates having an input node and output node and operated by an operating voltage which is lower than the standard operating voltage. At least one of the VDDH gates is multiple input gate. An output node of the VDDH gate or primary input terminal operated by the standard operating voltage is connected to at least one of the input nodes of the multiple input gate. The VDDL gate or the primary output terminal operated at the operating voltage which is lower than the standard operating voltage is connected to at least one of the other input nodes of the multiple input gate through a level converter.

REFERENCES:
patent: 5517132 (1996-05-01), Ohara
patent: 5594368 (1997-01-01), Usami
patent: 5818256 (1998-10-01), Usami
patent: 5920089 (1999-07-01), Kanazawa et al.
patent: 5926396 (1999-07-01), Ohara
Jui-Ming Chang and Pedram, M., "Energy Minimization Using Multiple Supply Voltages", International Symposium on Low Power Electronics and Design, 1996, pp. 157-162, Aug. 1996.
Chang, J., and Pedram, M., "Energy Minimization Using Multiple Supply Voltages", Proceedings of the International Symposium on Low Power Electronics and Design, 1996, pp. 157-162, Aug. 14, 1996.
How-Rern Lin and Ting Ting Hwang, "Power Reduction by Gate Sizing with Path-Oriented Slack Calculation", Proceedings of the Asian and South Pacific Design Automation Conference, 1995, pp. 7-12, Sep. 1, 1995.
Usami, K., and Horowitz, M., "Clustered Voltage Scaling Technique for Low-power Design", Proceedings of the International Symposium on Low Power Design, 1995, pp. 3-8, Apr. 1995.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Combinational logic circuit, its design method and integrated ci does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Combinational logic circuit, its design method and integrated ci, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Combinational logic circuit, its design method and integrated ci will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1007055

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.