Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-07-03
2007-07-03
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
10995658
ABSTRACT:
An equivalence checking method provides first and second logic functions. Don't care gates are inserted for don't care conditions in the first and second logic functions. The insertion of the don't care gates creates a first intermediate circuit and a second intermediate circuit. All 3DC gates of the first intermediate circuit are propagated and merged into a single 3DC gate when 3DC gates and SDC gates coexist in either of the first and second intermediate circuits. All 3DC gates of the second intermediate circuit are propagated and merged into a single 3DC gate when 3DC gates and SDC gates coexist in either of the first and second intermediate circuits. First and second circuit are produced in response to propagating and merging the 3DC gates. A combinational equivalence check is then performed of the first circuit to the second circuit under different equivalence relations.
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Chang Chioumin
Chen Kung-Chien
Lai Yung-Te
Lin Chih-Chang
Cadence Design Systems Inc.
Heller Ehrman LLP
Siek Vuthe
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