Combination test structures for in-situ measurements during fabr

Details Combination test structures for in-situ measurements during fabr Combination test structures for in-situ measurements during fabr

1999-12-09

2000-11-21

Ngo, Ngan V.

Active solid-state devices (e.g., transistors, solid-state diode

Test or calibration structure

257401, H01L 2358, H01L 2976, H01L 2994, H01L 31062, H01L 31113

Patent

active

061506699

ABSTRACT:
A first test structure (40) is used to measure both the gate resistance/linewidth and transistor performance. A gate line (42) crosses a moat region (44) with source (48) and drain (50) regions formed on either side of the gate line (42). The gate line (42) is connected to four probe pads (52) in an H configuration for accurate linewidth measurements. A second test structure (70) may be used alone or in conjunction with the first test structure. A single gate line (72) crosses a moat region (74) several times. This allows both capacitance and gate gate-resistance measurements with the same test structure and for more accurate TLD measurement.

REFERENCES:
patent: 5886363 (1999-03-01), Hamada et al.
patent: 5962868 (1999-10-01), Tanida
patent: 5982042 (1999-11-01), Nakamura et al.
patent: 6031246 (2000-02-01), Hamada et al.

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