Combination of global clock and localized clocks

Details Combination of global clock and localized clocks Combination of global clock and localized clocks

1999-11-03

2001-02-20

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S093000, C326S101000

Reexamination Certificate

active

06191609

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to semiconductor integrated circuits, and more particularly, to a combination of a global clock and localized clocks.
BACKGROUND OF THE INVENTION
A programmable logic device (PLD) is a standard product which can be purchased by systems manufacturers in a “blank” state and, thereafter, custom-configured into a virtually unlimited number of specific logic functions by programming the device. Because programmable logic devices provide great flexibility, these devices can be incorporated into a variety of systems.
The performance at which any such system can be operated is a function, at least in part, of the set-up time (T
SU
) and clock-to-output delay time (T
CO
) of the clock signals supplied to programmable logic device. The set-up time is the amount of time that information or data must be present at an input terminal before it can be latched and stored in the input registers of the programmable logic device. The clock-to-output delay time is the time that it takes for data to be present at an output terminal after a clock occurs. The operating frequency for the device is limited by the reciprocal of the sum of the set-up time and the clock-to-output delay time. This relationship is set out in the following equation:
ƒ
OP
≦1/(T
SU
+T
CO
)
where, ƒ
OP
is the operating frequency. Consequently, in order to maximize the operating frequency for the system, and hence, its performance, both the set-up time and the clock-to-output delay time should be minimized.
With previously developed techniques, however, the set-up time for a programmable logic device can not be decreased without producing a corresponding increase in the clock-to-output delay time. This is due to the fact that in a previously developed programmable logic device, a single global clock is used to drive both input and output signals at all locations of the device. A clock distribution structure comprising various lines, buffers, and other circuitry distributes the global clock so that it can be presented substantially simultaneously to all parts of the logic device. With this distribution, a delay in the global clock is created. This delay affects both the set-up time and the clock-to-output delay time. In particular, the set-up time can be decreased if the delay is longer. However, a longer delay in the global clock causes the clock-to-output delay time to be increased. Accordingly, any improvement in performance that would otherwise be provided by a decrease in set-up time is offset by a corresponding increase in clock-to-output delay time.
SUMMARY
The disadvantages and problems associated with previously developed programmable logic devices have been substantially reduced or eliminated using the present invention.
In accordance with an embodiment of the present invention, a programmable logic device includes a global clock structure and a plurality of localized clock structures. The global clock structure distributes a global clock signal throughout the programmable logic device. Each localized clock structure distributes a respective localized clock signal to a corresponding portion of the programmable logic device.
Important technical advantages of the present invention include providing both a global clock and a number of localized clocks on a programmable logic device. Each of the localized clocks is distributed and available only to a respective portion of the programmable logic device. The global clock is distributed throughout the device and available to all portions. The localized clocks and the global clock may each experience some delay, but the delay for the localized clocks will be less due to the smaller areas of distribution. Preferably, the global clock is used to drive input registers for the programmable logic device, while the localized clocks are used to drive output registers in the respective portions. Thus, the input data set-up time for the programmable logic device is determined by the global clock, whereas the clock-to-output delay time is determined by the localized clocks. Specifically, the set-up time is the time that data must be applied to the device input before the active edge of the global clock is applied to the global clock input. The clock-to-output delay time is the time it takes for data to appear at the device output after the local clock is applied to the local clock input. The set-up time can be decreased due to the longer delay of the global clock. Furthermore, due to the shorter delay and independence of the localized clocks, the clock-to-output delay time can be decreased as well. Accordingly, a system incorporating the programmable logic device may be operated at a higher frequency, thereby enhancing performance.
Other important technical advantages are readily apparent to one skilled in the art from the following figures, descriptions, and claims.


REFERENCES:
patent: 4903223 (1990-02-01), Norman et al.
patent: 4912342 (1990-03-01), Wong et al.
patent: 5140184 (1992-08-01), Hamamoto et al.
patent: 5396129 (1995-03-01), Tabira
patent: 5668484 (1997-09-01), Nomura

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