Combination flash memory and dram memory board interleave-bypass

Details Combination flash memory and dram memory board interleave-bypass Combination flash memory and dram memory board interleave-bypass

1997-06-16

1999-10-12

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711104, 711105, 395281, G06F 1202

Patent

active

059667273

ABSTRACT:
A memory board which functions as a main memory of a CPU, is accessible at high speed and is usable in a disk manner is proposed. A flash memory and a D-RAM are mounted on the memory board. The flash memory has a S-RAM interface which synthesizes a row address and a column address transmitted via an address bus, through a latch circuit or a signal processing circuit, to define an address. The CPU, when accessing an address in the flash memory, converts an address signal using an interleave rule in reverse, and transmits the converted address to a system logic. As a result, data can be written into contiguously allotted addresses in the flash memory. The flash memory can thus be used in a disk-like manner.

REFERENCES:
patent: 5335340 (1994-08-01), Strong
patent: 5341489 (1994-08-01), Herberger et al.
patent: 5463742 (1995-10-01), Kobayashi
patent: 5513135 (1996-04-01), Dell et al.

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