Combination erase waveform to reduce oxide trapping centers...

Details Combination erase waveform to reduce oxide trapping centers... Combination erase waveform to reduce oxide trapping centers...

2002-03-19

2003-09-02

Mai, Son (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185190, C365S185260, C365S185270

Reexamination Certificate

active

06614693

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to a class of non-volatile memory devices referred to as flash electrically erasable programmable read-only memory (flash EEPROM). More particularly, this invention relates to methods and means to erase digital data from a flash EEPROM cell and for eliminating trapped charges from the flash EEPROM cell to prevent closure of the difference of the programmed threshold voltage and the erase threshold voltage of the flash EEPROM cell.
2. Description of Related Art
The structure and application of the flash EEPROM is well known in the art. The Flash EEPROM provides the density advantages of an erasable programmable read-only memory (EPROM) that employs ultra-violet light to eliminate the programming with the speed of a standard EEPROM.
FIG. 1
a
illustrates a cross-sectional view of a flash EEPROM cell of the prior art. The flash EEPROM cell
10
is formed within a p-type substrate
12
. An n
+
drain region
14
and an n
+
source region
16
are formed within the p-type substrate
12
.
A relatively thin gate dielectric
36
is deposited on the surface of the p-type substrate
12
. The thin gate dielectric
36
will also be referred to as a tunneling oxide, hereinafter. A poly-crystalline silicon floating gate
32
is formed on the surface of the gate dielectric
36
above the channel region
34
between the drain region
14
and source region
16
. An interpoly dielectric layer
30
is placed on the floating gate
32
to separate the floating gate
32
from a second layer of poly-crystalline silicon that forms a control gate
28
.
A p
+
diffusion
18
is placed in the p-type substrate
12
to provide a low resistance path from a terminal
20
to the p-type substrate. The terminal
20
will be attached to a substrate voltage generator Vsub. In most application of an EEPROM, the substrate voltage generator Vsub is set to the ground reference potential (0V).
The source region
16
is connected to a source voltage generator VS through the terminal
22
. The control gate
28
will be connected through the terminal
26
to the control gate voltage generator VG. And the drain region
14
will be connected through the terminal
24
to the drain voltage generator VD.
According to conventional operation, the flash EEPROM cell
10
is programmed by setting the gate control voltage generator VG to a relatively high voltage (on the order of 10V). The drain voltage generator VD is set to a moderately high voltage (on the order of 5V), while the source voltage generator VS is set to the ground reference potential (0V).
With the voltages as described above, hot electrons will be produced in the channel
34
near the drain region
14
. These hot electrons will have sufficient energy to be accelerated across the gate dielectric
36
and trapped on the floating gate
32
. The trapped hot electrons will cause the threshold voltage of the field effect transistor (FET) that is formed by the flash EEPROM cell
10
to be increased by three to five volts. This change in threshold voltage by the trapped hot electrons causes the cell to be programmed.
During the programming process, some of the hot electrons will be trapped
42
in the tunneling oxide
36
or in surface states
40
at the surface of the p-type substrate
12
. These trapped electrons will cause the threshold voltage of the erased flash EEPROM cell
10
to increase.
To erase the flash EEPROM cell
10
as described in U.S. Pat. No. 5,481,494(Tang et al.), as shown in
FIG. 2
a
, a moderately high positive voltage (on the order of 5V) is generated by the source voltage generator VS. Concurrently, the gate control voltage generator VG is set to a relatively large negative voltage (on the order of −10V). The substrate voltage generator VS are set to the ground reference potential. The drain voltage generator VD is usually disconnected from the terminal
24
to allow the drain region
14
to float. Under these conditions there is a large electric field developed across the tunneling oxide
36
in the source region
16
. This field causes the electrons trapped in the floating gate
32
to flow to portion of the floating gate
32
that overlaps the source region
16
. The electrons are then extracted to the source region
16
by the Fowler-Nordheim tunneling.
Further Tang et al. shows a method for tightening the threshold voltage V
T
distribution of an array of flash EEPROM cells. The moderately high positive voltage (5V) that is applied to the source regions of the array of flash EEPROM cells and the relatively large negative voltage that is applied to the control gate insure a tighter distribution of the thresholds of the array of cells. The value of a load resistor between the low positive voltage and the source region is simultaneously reduced to a predetermined value so as to compensate for the increased erase time caused by the lowering of the magnitude of the negative constant voltage.
Referring back to
FIG. 1
a
during the erasure process, as a result of band to band tunneling, some positive charges or “hot holes”
38
will be forced and trapped in the tunneling oxide
36
. These trapped positive charges or “hot holes”
38
will cause the threshold voltage of the programmed flash EEPROM cell
10
to decrease. As can be shown in
FIG. 2
e
, after repeatedly performing write/erase cycling, the combination of the decrease
52
in the programmed threshold voltage
50
and the increase
57
in the erased threshold voltage
55
will cause the separation of the programmed threshold voltage
50
and the erased threshold voltage
55
to close until the flash EEPROM cell
10
fails. At this time, the flash EEPROM will no longer be able to operate reliably to store digital data.
FIG. 1
b
illustrates an alternate cross-sectional view of a flash EEPROM cell of the prior art. The flash EEPROM cell
10
is formed within a P-type substrate
12
. An N-type material is implanted within the P-type substrate
12
to a lightly doped concentration to for the N-well
47
. Within the N-well
47
, a P-type material is implanted to a lightly doped concentration to form the P-well
45
. An N
+
drain region
14
and an N
30
source region
16
are formed within the P-type well
45
.
A relatively thin gate dielectric
36
is deposited on the surface of the P-type substrate
12
. The thin gate dielectric
36
will also be referred to as a tunneling oxide, hereinafter. A poly-crystalline silicon floating gate
32
is formed on the surface of the gate dielectric
36
above the channel region
34
between the drain region
14
and source region
16
. An interpoly dielectric layer
30
is placed on the floating gate
32
to separate the floating gate
32
from a second layer of poly-crystalline silicon that forms a control gate
28
.
A P+ diffusion
18
is placed in the P-type substrate
12
to provide a low resistance path from a terminal
20
to the P-type substrate. The terminal
20
will be attached to a substrate voltage generator VSub. In most application of an EEPROM, the substrate voltage generator VSub will be set to the ground reference potential (0V).
The source region
16
will be connected to a source voltage generator VS through the terminal
22
. The control gate
28
will be connected through the terminal
26
to the control gate voltage generator VG. And the drain region
14
will be connected through the terminal
24
to the drain voltage generator VD. The P-well
45
is connected to a P-well voltage generator VPw through terminal
44
. The N-well
47
is connected to the N-well voltage generator VNw through the terminal
46
.
According to conventional operation, the flash EEPROM cell
10
is programmed by setting the gate control voltage generator VG to a relatively high positive voltage (on the order of 10V). The drain voltage generator VD is set to a moderately high voltage (on the order of 5V), while the source voltage generator VS and the P-well voltage generator VPw are set to the ground reference potential (0V). The N-well vo

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