Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
1998-12-23
2002-08-06
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S690000, C438S691000, C438S693000, C438S706000, C438S710000, C438S724000, C438S745000, C438S757000
Reexamination Certificate
active
06429132
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to a method for planarizing wafer-based integrated circuits, and more particularly to a novel method for planarizing the surface of an integrated circuit having optical elements disposed thereon. Even more particularly, the invention relates to a novel method for planarizing the reflective surface of a wafer-based, reflective light-valve backplane.
2. Description of the Background Art
Wafer-based reflective light-valves have many advantages over their transmissive predecessors. For example, conventional transmissive displays are based on thin-film transistor (TFT) technology, whereby the displays are formed on a glass substrate, with the TFTs disposed in the spaces between the pixel apertures. Placing the driving circuitry between the pixel apertures limits the area of the display available for light transmission, and therefore limits the brightness of transmissive displays. In contrast, the driving circuitry of reflective displays is located under reflective pixel mirrors, and does not, therefore, consume valuable surface area of the display. As a result, reflective displays are more than twice as bright as their transmissive counterparts.
Another advantage of wafer-based reflective displays is that they can be manufactured with standard CMOS processes, and can therefore benefit from modem sub-micron CMOS technology. In particular, the reduced spacing between pixel mirrors increases the brightness of the display, and reduces the pixelated appearance of displayed images. Additionally, the CMOS circuitry switches at speeds one or more orders of magnitude faster than comparable TFT circuitry, making wafer-based reflective displays well suited for high speed video applications such as projectors and camcorder view finders.
FIG. 1
is a cross-sectional view of a prior art reflective display backplane
100
, which is formed on a silicon substrate
102
, and includes a layer
104
of integrated circuitry, an insulating support layer
106
, a plurality of pixel mirrors
108
, and a protective oxide layer
110
. Each of pixel mirrors
108
is connected, through an associated via
112
, to the circuitry of layer
104
. Backplane
100
is typically incorporated into a reflective light valve (e.g., a liquid crystal display) by forming a layer
114
of an optically active medium (e.g., liquid crystal) over the pixel mirrors, and forming a transparent electrode (not shown) over the optically active medium. Light passing through the medium is modulated (e.g., polarization rotated), depending on the electrical signals applied to pixel mirrors
108
.
One problem associated with prior reflective displays is that the generated images often appear mottled. One source of mottling in reflective displays is the non-uniform alignment of the liquid crystals in layer
114
. The formation of liquid crystal layer
114
typically includes a wiping or rubbing step, wherein a roller or similar object is passed over the liquid crystal layer, resulting in alignment of the liquid crystals. However, pixel mirrors
108
project upward from the surface of backplane
100
, defining gaps between adjacent pixel mirrors. Known wiping processes are ineffective to align the liquid crystals (represented by arrows in layer
114
) in these gaps. Additionally, the misaligned crystals adversely affect the alignment of neighboring crystals in layer
114
.
What is needed is a reflective backplane with a planar surface to facilitate the effective alignment of the entire liquid crystal layer.
FIG. 2
is a cross sectional view of a reflective backplane
200
, illustrating the ineffectiveness of a method of planarizing the surface of reflective backplane
200
by depositing a thick protective oxide layer
202
and then etching layer
202
back to a desired thickness level
204
. In particular, as oxide layer
202
is deposited, the opening
206
to the gap between pixel mirrors
108
closes before the gap is filled. This is known to those skilled in the art as the “keyhole effect.” Then when oxide layer
202
is etched back to level
204
, a nonplanar defect
208
remains over the partially filled gap, and will frustrate the uniform alignment of layer
114
.
FIG. 3
is a cross sectional view of a reflective display backplane
300
illustrating an anticipated problem of using a prior art planarization process on a reflective backplane. Backplane
300
is planarized by forming a thick oxide layer
302
over pixel mirrors
108
and the portion of support layer
106
exposed by the gaps between pixel mirrors
108
. Thick oxide layer
302
can only be formed without the keyhole effect shown in
FIG. 2
, if pixel mirrors
108
are sufficiently thin (e.g., less than 1000 angstroms). After its application, thick oxide layer
302
is ground down to a planar level
304
, by a prior art process known as chemical-mechanical polishing (CMP). This process, also referred to as chemical-mechanical planarization, and is well known to those skilled in the art.
This method of planarizing the surface of reflective backplane
300
suffers from the disadvantage that it is limited to layers having a thickness of greater than or equal to 1,000 angstroms. That is, the CMP process is incapable of leaving an oxide layer of less than 1,000 angstroms over pixel mirrors
108
. This planarization method is, therefore, not well suited for planarizing substrates having optical elements disposed on their surface, because the thickness of the film remaining on the optical element is often critical to its proper optical functionality.
What is needed is a method for planarizing the surface of substrates having optical elements disposed on their surface, that is capable of leaving layers over the optical elements, having a thickness of less than 1,000 angstroms.
SUMMARY
The present invention overcomes the limitations of the prior art by providing a novel method for planarizing a substrate (e.g., a reflective display backplane) including a plurality of surface projections (e.g., pixel mirrors) and thin surface films (e.g., optical thin film coatings). Where the substrate is a reflective display backplane, the resulting planar surface reduces mottling in projected images.
A disclosed method includes the steps of forming an etchable layer on the substrate, performing a CMP process on the etchable layer to form a planar layer having a first thickness (e.g., >1,000 Angstroms), and etching the planar layer to a second thickness (e.g., <1,000 Angstroms). In a particular method, the substrate is an integrated circuit and the projections are optical elements. In a more particular method, the substrate is a reflective display backplane, and the projections are pixel mirrors.
In a particular method suitable for planarizing substrates having surface projections in excess of 1,200 Angstroms, the step of forming the etchable layer includes the steps of forming an etch-resistant layer on the substrate, forming a fill layer on the etch-resistant layer, etching the fill layer to expose portions of the etch resistant layer overlying the projections and to leave a portion of the fill layer in the gaps, and forming the etchable layer on the exposed portions of the etch-resistant layer and the fill layer.
The etch resistant layer may include an optical thin film layer, and may be formed as a single layer. Optionally, the etch resistant layer includes a plurality of sublayers, for example an optical thin film layer and an etch resistant cap layer. In a particular method, the step of forming the etch resistant layer includes a step of forming an oxide layer and a second step of forming a nitride layer on the oxide layer.
The step of forming a fill layer on the etch resistant layer may include the step of applying a spin-on coating (e.g., spin-on glass) over the etch resistant layer. Optionally, the fill layer includes a suitable dopant to absorb light of a particular wave length.
One particular method of the present invention further includes an optional step of forming a protective layer over th
Haskell Jacob Daniel
Hsu Rong
Aurora Systems, Inc.
Brown Charlotte A.
Henneman & Saunders
Henneman, Jr. Larry E.
Utech Benjamin L.
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