Column voltage control for write

Details Column voltage control for write Column voltage control for write

2003-01-06

2004-09-14

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000, C365S206000

Reexamination Certificate

active

06791864

ABSTRACT:

FIELD OF THE INVENTION
The present invention is generally related to memory integrated circuits, and more particularly to SRAM cells and noise margin problems during write.
BACKGROUND OF THE INVENTION
In a memory cell array, generally one row of cells and a subset of the columns are addressed in a WRITE cycle. With scaling (L, Vdd and Vt), it is increasingly difficult to design SRAM cells that have enough stability i.e. noise margin (SNM) (resistance to upset) but still can be written into. Generally, design variations that improve stability degrade the ability to WRITE (Vtrip).
Referring to
FIG. 1
there is shown at
10
a conventional SRAM memory cell
10
seen to have a wordline (WL), supply voltages Vdd and Vss, and bit-lines B and B_. Conventionally, during a READ cycle, the wordline WL is high, both bit-lines B and B_are precharged high, and the access transistor pulls against the driver. Either a strong pass or a weak load leads to destabilization of the cell
10
during a READ cycle.
For a WRITE cycle, the wordline WL is high, bit-line B is high and bit-line B_is low, or vise-versa. Here, the access transistor pulls against the load, whereby a strong pass and weak load enables the WRITE.
SUMMARY OF THE INVENTION
The present invention achieves technical advantages as a memory device including a memory cell array having an array Vdd bussed such that the Vdd of columns are controlled independently. In a WRITE cycle, the Vdd of the addressed columns is lowered. Thereafter, the access transistor is turned on more strongly with the wordline WL at array Vdd than is the load transistor at the reduced column Vdd, and the cell is advantageously more easily written. Cells in other columns in the addressed row remain at array Vdd and are more stable. Cells in un-addressed rows in the addressed columns will not have the access transistors turned on, and therefore will be more stable. With WRITE being facilitated with a lowered column Vdd, the cell is designed to be more stable than would otherwise have been possible while maintaining the ability to WRITE.
The present invention relieves the trade-off of stability and ability to WRITE to a memory cell. There is provided the enhanced ability to WRITE with fairly simple circuitry while achieving a more stable cell. The cells operate over a wider range of supply voltage and temperature, and/or a wider range of process parameters.


REFERENCES:
patent: 6147898 (2000-11-01), Yamada
patent: 2003/0214833 (2003-11-01), Hsu et al.

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