Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2002-05-15
2003-12-02
Le, Thong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S225700
Reexamination Certificate
active
06657907
ABSTRACT:
RELATED APPLICATION
This application claims the benefit of Korean Patent Application No. P2001-26369 filed on May 15, 2001, under 35 U.S.C. §119, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a redundancy circuit of a semiconductor memory, and more particularly, to a column repair circuit of a semiconductor memory capable of increasing its repair yield in a row flexible redundancy structure.
2. Discussion of the Related Art
Generally, in a semiconductor memory, a redundancy circuit and a redundancy memory cell array for repairing a defective memory cell using a redundancy memory cell are provided.
A redundancy operation is performed by separately providing a redundancy memory cell array besides a normal memory cell, by decoding an input address which designates a certain defective memory cell in a normal memory cell array, and then by selecting a redundancy row or a redundancy column connected to the redundancy memory cell.
The redundancy operation is performed by a redundancy decoder. An output signal of the redundancy circuit which programs a defective address determines whether or not a normal decoder or a redundancy decoder is enabled. The redundancy circuit programs the defective address by laser-cutting a fuse provided inside the redundancy circuit according to an address which will be decoded.
A column redundancy circuit has to quickly determine which column to select between a redundancy column and a normal column each time a column address is input. In a semiconductor memory circuit, if an address for designating a defective column is input, the input address is replaced with the address of a redundancy column so as to repair the defective column, and the redundancy column is selected.
A related art column repair circuit of a semiconductor memory will be explained with reference to the accompanying drawings.
FIG. 1
illustrates a schematic view of a general semiconductor memory cell array, and
FIG. 2
illustrates a schematic view of a related art column repair.
FIG. 3
illustrates a block diagram showing a construction of a related art column fuse box, and
FIG. 4
illustrates a schematic view showing a problem at the time of repairing a related art column.
Generally, as shown in
FIG. 1
, a cell array consists of arrays having a plurality of cells, word lines, and column selective lines. Herein, the word lines and the column selective lines cross each other.
For a column repair of the cell array, as shown in
FIG. 2
, redundant column lines are formed at margin portions of the array, not at a middle portion of the array. To improve a column repair efficiency in this structure, the entire column selective lines are not replaced, but only the when column selective line(s) corresponding to the failed array are replaced.
That is, as shown in
FIG. 2
, when a column line (column selective line) YI<0> in an array
1
fails, a redundant column line SYI<0> is selected if the column line YI<0> is selected in a column cycle once the array
1
is selected in a low cycle. In the same manner, when a column line YI<1> in an array
3
fails, a redundant column line SYI<0> is selected if the column line YI<1> is selected in a column cycle once the array
3
is selected in a low cycle. As a result, in the convention art, a plurality of column lines YI<0> . . . YI<n> are replaced with only one redundant column line SYI<0>.
Herein, the number of times that the same redundant column line SYI is used to replace different failed column lines is determined by the number of programming fuse boxes assigned to the redundant column line SYI in case that a column failure occurs in different arrays.
A structure of a related art programming fuse box will now be explained referring to FIG.
3
.
As shown in
FIG. 3
, each of a plurality of column fuse boxes
30
includes an array address fuse and latch box
32
for evaluating and latching a fuse in response to a row cycle timing signal and an array address input thereto; a column address fuse box
33
for outputting a column redundant signal based on an output signal of the corresponding array address fuse and latch box
32
, an externally input column cycle timing signal, and a column address.
The column redundant signals output from the respective column address fuse boxes
33
of the column fuse boxes
30
are processed by an OR operation of an OR gate
31
. The OR gate
31
finally outputs a redundant column enable signal.
It is known that a row repair algorithm method used in a flexible redundancy algorithm improves a row repair efficiency by replacing a failed word line in one array, not only with a redundant word line in the corresponding array but also with a redundant word line in another array. However, in the case where a column failure in the replaced array (for correcting a word line failure) is detected, there is no method for repairing such column failure. The reason is because the replacement is made only when a failed array address is provided in a row cycle at the time a spare column line is selected to improve the efficiency of a column failure. In a related art row repair method, when a column failure occurs, only a redundant line in a block where the column failure occurs is used to replace the failed column line.
Thus, at this time, there are at least the following problems.
If it is assumed that a number of prepared redundant row lines are 4 per one block, a repair cannot be performed in a case where more than 4 row line failures occur in one array. This inhibits the use of the entire chip.
A flexible redundant structure allows the use of not only the array where a failure occurred but also the use of a redundant line in another array to solve the line failure problems. In this process, an array where the failure occurred is called a “self” array, and another array that provides a redundant line for the self array is called a “pair” array.
FIG. 4
illustrates a schematic view showing a problem at the time of repairing a related art column line, in which a row line having a failure in a self array is replaced with a redundant word line of a pair array. However, if a corresponding column address is selected where a failed column line is found in the pair array, the array address of the self array, instead of the array address of the pair array, is input since the pair array has a failed column line, whereby the failed column line is not replaced.
The above problem occurs even though the redundancy circuit is programmed so that a failed column is to be replaced with a redundant column in the pair array.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a column repair circuit for a semiconductor memory that substantially obviates one or more problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a column repair circuit of a semiconductor memory which can increase efficiency of a column repair in a row flexible redundancy structure.
Another object of the present invention is to provide a column repair device for a memory which receives information and generates an address of a replaced array when a row repair in the column repair device is replaced not in its array where the failure of a word line occurred but in another array.
According to an aspect of the present invention, when a failure of a column line occurs in a replaced array, an occasion in which a failure occurs again for the replaced word line can be prevented.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve t
Hynix / Semiconductor Inc.
Le Thong
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