Electronic digital logic circuitry – Reliability – Redundant
Reexamination Certificate
1999-09-15
2001-09-18
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Reliability
Redundant
C326S037000, C326S041000
Reexamination Certificate
active
06292013
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to memories generally and, more particularly, to a column redundancy scheme for bus-matching FIFOs.
BACKGROUND OF THE INVENTION
Column redundancy is used in the fabrication of memory devices to improve the overall yield of the fabrication process. If a column, or a number of columns, are found to be defective during the testing of the device, one or more redundant columns can be substituted for the defective columns. The substitution allows the device to function properly despite the defective columns.
Bus-matching features, such as those found in co-pending application U.S. Ser. No. 60/102,035, filed on Sep. 28, 1998, which is hereby incorporated by reference in its entirety, make the implementation of column redundancy much more complex than column redundancy in traditional FIFOs.
Conventional column redundancy circuits, which would require fuses to configure a circuit that multiplexes the data into and out of the faulty memory section to enable the redundant column, do not work with the bus-matching circuit of the co-pending application, since there is not generally a layer of multiplexers to implement such fusing.
SUMMARY OF THE INVENTION
The present invention concerns a circuit and method comprising a multiplexer circuit, a select circuit and a buffer circuit. The multiplexer circuit may be configured to present a data bit in response to a first control signal. The select circuit may be configured to generate one or more first outputs in response to (i) said data bit and (ii) one or more first select signals. The buffer circuit may be configured to present one or more second outputs on a data bus in response to (i) said one or more first outputs and (ii) one or more second control signals. One of the second outputs may have a data state and the rest of the second outputs may have a high impedance state. The first and select signals may be generated by a logic circuit.
The objects, features and advantages of the present invention include providing a column redundancy circuit and/or logic that may be implemented in a bus-matching circuit that may (i) use less area to implement by reducing the number of fuses incorporated into the main (non-redundant) datapath, (ii) be implemented independently of the main datapath, therefore incurring little to no impact to an existing datapath layout, and (iii) be less complex to implement by reducing the requirement of a complex fuse architecture and fuse-blowing procedures. The reduction of fuses is particularly useful where the layout is pitch-matched.
REFERENCES:
patent: 3473160 (1969-10-01), Wahlstrom
patent: 5689195 (1997-11-01), Cliff et al.
Cress Daniel Eric
Narayana Pidugu L.
Savage Derrick
Christopher P. Maiorana P.C.
Cypress Semiconductor Corp.
Tokar Michael
Tran Anh
LandOfFree
Column redundancy scheme for bus-matching fifos does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Column redundancy scheme for bus-matching fifos, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Column redundancy scheme for bus-matching fifos will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2443971