Column redundancy in semiconductor memories

Details Column redundancy in semiconductor memories Column redundancy in semiconductor memories

1997-07-31

1999-09-28

Le, Vu A.

Static information storage and retrieval

Read/write circuit

Bad bit

3652257, 36518902, 36523002, G11C 700

Patent

active

059599030

ABSTRACT:
This invention describes a column redundancy method and apparatus in a DRAM that minimizes the timing difference between a normal and redundant column paths and which minimizes the number of fuses required in repairing faulty columns. The invention discloses a DRAM having memory elements arranged in rows and columns, the memory elements being accessible by decoding a memory address applied thereto, normal column drivers for energizing appropriate memory columns in response to the decoder memory addresses received at an input thereof; redundant column drivers; and switch means for steering the decoded memory address onto one of either normal or redundant column driver paths. The invention further illustrates a fusing system which minimizes the capacitance of redundant select lines, thereby removing unnecessary delay in the redundant column path.

REFERENCES:
patent: 5282165 (1994-01-01), Miyake et al.
patent: 5325334 (1994-06-01), Roh et al.
patent: 5469391 (1995-11-01), Haraguchi et al.
patent: 5469401 (1995-11-01), Gillingham
patent: 5570318 (1996-10-01), Ogawa

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