Column redundancy for content addressable memory

Details Column redundancy for content addressable memory Column redundancy for content addressable memory

2002-06-18

2003-12-16

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S049130, C365S189070

Reexamination Certificate

active

06665220

ABSTRACT:

This application claims priority from Canadian Patent Application No. 2,360,897, filed Oct. 31, 2001.
FIELD OF THE INVENTION
The present invention relates to a method and apparatus for replacing defective elements with spare elements in an integrated circuit chip. More specifically, the present invention relates to implementing redundancy in a Content Addressable Memory (CAM).
BACKGROUND OF THE INVENTION
In the manufacture of memory systems for packaging in integrated circuit packages, a series of repetitive memory blocks is produced on a wafer. Each memory block is comprised of a number of memory elements. As a result of imperfections in the manufacturing process and in the materials used, it is not uncommon for memory elements in the memory blocks to be defective. If a block contains a defective memory element it is unable to be reliably accessed by the memory subsystem, thus the memory element must be either discarded or repaired to allow for reliable use of all accessible memory elements. While single, isolated memory element failures may be spread throughout the array, very often, multiple memory elements in the same vicinity fail. Since multi-memory element failures occur in the same vicinity, a column containing at least one faulty element is usually deemed to be defective and will have to be somehow replaced with a functional row or column.
Row and/or column redundancy is used in most semiconductor memory devices to address the problem of defective memory elements. The most common implementation of redundancy is column redundancy, which provides an on-chip system for replacing a predetermined number faulty columns with functional columns, thereby allowing the repair of defective memory elements. Typically, redundant elements are placed adjacent to the normal elements in the array, so these redundant elements and the associated control circuitry occupy additional silicon area adjacent to the area occupied by the normal memory elements and their associated control circuits. Increasing the number of redundant elements increases the yield of the manufacturing process, at the expense of more costly circuits and increased circuit area. As a result, a trade-off exists between the number of redundant elements to provide on the chip and the overall chip area.
The addition of redundant memory elements in order to improve IC yield in the manufacturing process for Random Access Memory (RAM) is known. Very often, chips with defective memory elements can be repaired prior to being packaged. Once identified, defective memory elements can be replaced with spare memory elements, usually by programming the faulty address or addresses into fuse banks, or other types of non-volatile memory, which then re-route the address or data path from a normal path to a redundant path. For example, in a given block of RAM on a wafer there are a number of identical memory elements. If one memory element is found to be defective, the faulty address is programmed into an on-chip fuse programming circuit, and all normal address or data path connections to that memory element are routed to a redundant memory element. Though this technique is incapable of guaranteeing a 100% yield, it is known to dramatically increase the yield with a limited number of redundant memory elements. The increase in yield is proportional, but not linearly related, to the number of redundant memory elements provided.
Many implementations of redundancy have been applied to the production of RAM. One such example, for use with RAMs with very wide data bus widths (for example 128 bits), is U.S. Pat. No. 5,796,662, entitled “Integrated circuit chip with a wide I/O memory array and redundant data lines”, to Kalter et al. This patent teaches a bit-shift redundancy system which includes a data word input block for switching defective elements out of the data path, thereby steering data destined for the defective elements bits either to left or right adjacent elements, as well as an output shift block to shift the non-defective bits back into position. In this manner, the data bit order is maintained even after a defective element has been replaced. The input and output shift blocks are comprised of three-way CMOS switches which selectively steer data through either one of the three possible paths associated with each switch. This provides a column redundancy system which effectively bypasses defective elements, and replaces them with identical adjacent elements rather than replacing defective elements with redundant elements which may have a different activation time than the activation time of normal elements. The problem with this approach is that each time a defective address is specified, the entire data word must be shifted over by one or more bit positions in order to avoid the defective column and then, the entire word has to be re-shifted back into position in order to maintain the overall bit order. This requires two sets of three-way switches associated with each bit in the data word and requires a lot of area. In addition, the adjacent shifting of elements to the right or left of defective elements and then the subsequent re-shifting back into position of the non-defective elements introduces a propagation delay in the data path.
Although the use of redundancy in content addressable memories (CAM) has been proposed, its use is more limited than in commodity RAMs. Row redundancy schemes for CAM have been proposed but column redundancy is more challenging. Conventional column decoding used in DRAMs where wherein a small group or a single column is selected by a column decoder does not readily apply to CAMs having very wide word width. In such cases, redundancy based on column addressing is not effective since individual bits within a very wide word cannot be individually addressed. As a result, some type of data steering is preferable in attempting to implement column redundancy in CAMS. Furthermore for CAMs employing separate search and data paths, the implementation of redundancy becomes even more challenging since any changes in the data path must be correlated with associated changes in the search path. For example, the search path may allow searching of the entire CAM simultaneously whereas the read/write data path typically can only access a subset of the entire CAM at any one time. This simultaneous search and read/write access is difficult to implement if for example a programmable register were used to track defective memory elements and the associated replacement element since any coding or scrambling of the defective cell information has to be performed in both the data (and/or address) path as well as in the search path.
Another factor complicating the implementation of redundancy in the context of CAMs is that the search line is typically connected to multiple other CAM elements, and each CAM element contributes a known parasitic capacitance to the search line (it will be readily understood by one skilled in the art that although we refer to a search line being connected to a memory element, in the case of ternary content addressable memory there is in fact typically a pair of search lines connected to each ternary memory cell in order to allow ternary data storage as well as search and compare capability). The magnitude of the parasitic capacitance contributed to the search line is crucial to the timing of memory operations, since the higher the parasitic capacitance of the search line, the longer it takes to switch the search line from one logic state to another.
Additionally it is possible that each CAM element imposes a different parasitic capacitance on the search line. A defective CAM column that is replaced, cannot simply be ignored by severing a search line because the parasitic capacitance of the local search line attached to the CAM column is essential to the proper operation of the global search line. Additionally it is not possible to leave the search line intact and ignore it, as the search line may take on a value that results in erroneous results on the memory system's search line.
U.S. Pat. N

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