Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1998-03-16
2001-03-20
Nguyen, Than (Department: 2759)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S101000, C711S105000, C711S170000, C711S173000, C711S152000, C714S040000, C714S041000, C714S042000
Reexamination Certificate
active
06205515
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to redundancy in memory circuits, and more particularly to accessing redundant columns.
2. State of the Art
Redundancy is used in memory systems having memory arrays to replace failed rows, columns, or single cells in the array. To implement redundancy in a memory system, spare (or redundant) replacement rows or columns and redundancy circuitry are designed into the memory structure. The redundancy circuitry functions to disable the failed row or column to be replaced as well as enable a redundant row or column such that when the failed row or column is accessed by its corresponding address, the redundant TOW is accessed instead.
FIG. 1
shows the conventional structure of a memory system
10
using column redundancy including a memory array
11
, sets of redundant columns
0
-N, and address decoder and redundancy circuitry
12
. The memory array
11
is divided into blocks of columns Block <
0
>, Block <
1
>, . . . Block <N> and each block includes a corresponding set of redundant columns
0
-N, respectively. Each block has a corresponding sense amplifier
13
for sensing data from its corresponding block and provides it to output
14
.
During a normal access operation, the address decoder provides a block select signal to select and enable data sensing from one of the N blocks in which the access operation is to occur, and provides column and row select signals to select and access the specific memory cells within the selected block.
The redundant circuitry
12
includes decode circuitry coupled to each redundant column. The decode circuitry includes the same number of fuses as bits in the column address. During device testing when a defective column is detected, its address is programmed into one of the redundant column's associated decode circuitry by blowing its fuses so as to match the defective column address. Programming the redundancy circuitry with the defective columns address also permanently disables the defective column such that the redundant column is accessed instead of the defective column.
In an access operation in which a defective column is being accessed, the address decoder provides a block select and enable signal to the block in which the defective column resides. However, when the defective column address is decoded by the address decoder and redundancy circuitry, the redundant column is accessed instead of the defective column. For instance, if a defective column in Block
1
is accessed, Block
1
is enabled but one of the redundant columns in redundant column set
1
is accessed instead of the defective column.
In the memory structure shown in
FIG. 1
having N blocks of columns each including a set of redundant columns, decode circuitry each having as many fuses as column address bits is required for each redundant column in each of the N sets of redundant columns. As can be imagined this redundancy design tends to consume significant wafer space.
In addition, another disadvantage of this type of design relates to the relative position of the blocks of columns and each block's associated access time. Specifically, address select signals and in particular row (or wordline) select signals are generated by the address decode. These signals are transmitted to each block along a single wordline address. As a result, due to the propagation time for the select signal to travel from the decode circuitry to each of the blocks, blocks that are farther from address decode (e.g. block N) receive the select signals later than closer blocks. Hence, the addition of redundant columns tends to extend out the farthest block position even more, thereby increasing the delay of select signals. Since each set of redundant columns exhibits the same access time as the block it resides in, if a column is replaced in the Nth block, then the redundant column will also exhibit the same approximate longer access time as the Nth block. Moreover, the extra capacitive loading caused by the redundant columns in each block slows sensing of data even more for all blocks and in particular the Nth block such that the overall access time for the device is increased still.
The present invention is a manner in which to incorporate redundancy into a memory system such that less space is used and the access time of redundant columns in the memory system is reduced.
SUMMARY OF THE INVENTION
The present invention is a memory system including redundancy for replacing defective columns in the memory array and method thereof. The memory system includes a memory array divided into a plurality of blocks of columns
0
-N and a single set of redundant columns residing within the block of columns which is either the fastest accessed block or the block which is located closest to the select signal generators (i.e., the address decode and the redundancy circuitry). Redundancy circuitry compares the input address to pre-programmed defect column addresses. If a match occurs, the redundancy circuitry provides a match signal that enables the fastest block for sensing data, selects a redundant column, deselects all regular columns in the fastest block, and disables all other blocks. If a match does not occur, an address decode portion decodes the input address and provides at least a block select signal, a column select signal and a row select signal for accessing the memory array in a normal access operation.
In one embodiment, row redundancy is incorporated into a memory system by adding redundant rows to the closest or fastest block, enabling only the closest or fastest block when a redundant row address matches an input row address, disabling all other blocks, disabling all of the enabled block rows, and enabling the redundant row.
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Burns Doane Swecker & Mathis L.L.P.
Nguyen Than
Winbond Electronic Corporation
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