Column redundancy circuit with reduced signal path delay

Details Column redundancy circuit with reduced signal path delay Column redundancy circuit with reduced signal path delay

1998-10-30

2000-10-24

Nelms, David

Static information storage and retrieval

Read/write circuit

Bad bit

36523003, 36523006, G11C 700

Patent

active

06137735&

ABSTRACT:
The invention discloses a synchronous DRAM having memory elements arranged in rows and columns, the memory elements being accessible by decoding a memory address applied thereto, normal column drivers for activating appropriate memory elements in response to decoded column addresses signals; redundant column drivers distributed throughout memory banks and flexibly selectable to replace faulty columns within multiple blocks within a bank; and switch means for selectively activating the redundant column and preventing the activation of a defective normal column, whereby the column redundancy method and apparatus minimizes the timing difference between a normal and redundant column paths and which minimizes the number of fuses required to be blown in repairing faulty columns addresses.

REFERENCES:
patent: 4691301 (1987-09-01), Anderson
patent: 5394368 (1995-02-01), Miyamoto
patent: 5621691 (1997-04-01), Park
patent: 5646896 (1997-07-01), Pinkham
patent: 5657279 (1997-08-01), Savignac et al.
patent: 5675543 (1997-10-01), Rieger
patent: 5732030 (1998-03-01), Dorney
patent: 5787046 (1998-07-01), Furuyama et al.

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