Column redundancy circuit for a memory device

Details Column redundancy circuit for a memory device Column redundancy circuit for a memory device

1998-09-15

1999-09-14

Mai, Son

Static information storage and retrieval

Read/write circuit

Bad bit

36523006, 36523002, G11C 700

Patent

active

059532700

ABSTRACT:
The present invention relates to a column redundancy circuit in semiconductor memories which improves yields by means of substituting defective cells with redundant memory cells provided that defective memory cells are detected. The present invention of a redundancy circuit in semiconductor memories having a first memory cell array and a second memory cell arrays with an Y-decoder includes a first row redundancy circuit receiving a row address signal wherein the first row redundancy circuit outputs a first MAT selection signal for repairing a word line in the first memory cell array, a second row redundancy circuit receiving the row address signal wherein the second row to redundancy circuit outputs a second MAT selection signal for repairing a word line in the second memory cell array, a redundancy circuit controller generating a first MAT selection enable signal and a second MAT selection enable signal wherein the first MAT selection enable signal and the second MAT selection enable signal are complementary each other, a MAT selection signal controller receiving the first MAT selection signal and the second MAT selection signal wherein the MAT selection signal controller outputs one of the first MAT selection signal and the second MAT selection signal in accordance with the first MAT selection enable signal and the second MAT selection enable signal, respectively, a column redundancy circuit receiving a column address signal and the MAT selection signal which is outputted from the MAT selection signal controller wherein the column redundancy circuit outputs a repairing decision signal, a first MAT redundant signal and a second MAT redundant signal, and an Y-decoder receiving the first MAT redundant signal and the second MAT redundant signal wherein the Y-decoder outputs a normal column selection signal or a redundant column selection signal under a condition of the repairing decision signal.

REFERENCES:
patent: 5475640 (1995-12-01), Kersh, III et al.
patent: 5495445 (1996-02-01), Proebsting
patent: 5570318 (1996-10-01), Ogawa
patent: 5621691 (1997-04-01), Park
patent: 5652725 (1997-07-01), Suma et al.
patent: 5835424 (1998-11-01), Kikukawa et al.

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