Column redundancy circuit

Details Column redundancy circuit Column redundancy circuit

2001-06-28

2002-12-03

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S230060

Reexamination Certificate

active

06490208

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a column redundancy circuit for a semiconductor memory device, and more particularly to an improved column redundancy circuit which can improve repair flexibility and efficiency without increasing column redundancy. It does so by providing information of a DQ having a defect to a column redundancy fuse box in order to repair a defect of another DQ.
2. General Background and Related Art
In general, when a cell in a cell array has a defect, a column redundancy circuit replaces a bit line connected to the cell by a spare bit line, thereby compensating for the defect. When an address of selecting the defect cell is internally applied to a device, a normal path of selecting the defect cell is intercepted, and a redundancy circuit is operated, thereby enabling the bit line connected to the repaired cell. Accordingly, the column redundancy operation is performed.
FIG. 1
(Prior Art) is a schematic diagram illustrating a conventional column redundancy circuit for a DRAM. The conventional column redundancy circuit includes DQ regions DQ
0
~DQn that are physically divided to access data, and have a plurality of normal cells
2
and a plurality of repair cells
3
. A column decoder unit
4
,
14
selects the normal cell
2
,
12
of the respective DQ regions DQ
0
~DQn. A repair column decoder unit
5
,
15
selects the repair cell
3
,
13
of the respective DQ regions DQ
0
~DQn. A write driver and read sense amp unit
6
,
16
having a write driver for driving data inputted through a global I/O line GIO<n> to a memory cell in a write operation, and a read sense amp for sensing and amplifying the data from the memory cell, and outputting the data to the global I/O line GIO<n> in a read operation.
When the DQ regions DQ
0
~DQn are physically divided from cell regions
1
,
11
, a local data bus LCD and a global data bus GDB share each other in their DQ, and thus the repair column cells
3
,
13
can repair a defect cell only in the DQ which they belong to.
Accordingly, the number of the repair cells must be increased to improve repair flexibility and efficiency of the conventional column redundancy circuit. However, in this case, a size of a chip is increased, which results in high production cost and low productivity.
SUMMARY
The claimed inventions feature, at least in part, a column redundancy circuit which can improve repair flexibility and efficiency without increasing column redundancy, by providing information of a DQ having a defect to a column redundancy fuse box so as to repair a defect of another DQ.
There is provided a column redundancy circuit including a plurality of DQ region units including a memory cell array unit having a plurality of cells sharing a local data bus and a global data bus. A column decoder unit generates a column decoding signal for selecting one of the cells. A write driver unit drives data inputted through a global I/O line to the global data bus. A read sense amp unit amplifies data inputted through the global data bus, and transmits the data to the global I/O line. A repair region unit including a repair cell array unit has a plurality of repair cells sharing the local data bus and the global data bus. N column decoder units generate a column decoding signal for selecting one of the repair cells. N write driver units drive data inputted through the global I/O line to the repair global data bus. N read sense amp units amplify data inputted through the repair global data bus, and transmit the data to the global I/O line. N DQ selection fuse box units program information of the DQ region unit having a defect cell among the plurality of DQ region units. N multiplexer and demultiplexer units switch one write driver unit among the N write driver units, one read sense amp unit among the N read sense amp units, and the global I/O line according to output signals from the DQ selection fuse box units.
The column redundancy circuit further includes N decoder units for decoding the output signals from the N DQ selection fuse box units, and outputting the decoded signals to the N multiplexer and demultiplexer units.


REFERENCES:
patent: 6067260 (2000-05-01), Ooishi et al.
patent: 6144591 (2000-11-01), Vlasenko et al.
patent: 6172916 (2001-01-01), Ooishi et al.
patent: 6314030 (2001-11-01), Keeth
patent: 2001/0026496 (2001-10-01), Hidaka

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