Column redundance circuit configuration for a memory

Details Column redundance circuit configuration for a memory Column redundance circuit configuration for a memory

1994-02-17

1995-10-10

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Bad bit

3652257, 371 103, G11C 700

Patent

active

054576555

ABSTRACT:
A column redundance circuit configuration for a memory includes a memory blocks with memory cells disposed in x lines and y columns. Redundant memory cells are disposed in b lines and c columns. A column decoder and c redundant column decoders are provided. Each column decoder is assigned to a respective one of the c redundant columns of each of the memory blocks. D encoding elements each have an address decoding device for assigning it to an arbitrary memory block.

REFERENCES:
patent: 5227997 (1993-07-01), Kikuda et al.
IEEE Journal of Solid-State Circuits, vol. 26, No. 1, Jan. 1991, pp. 12-17, (Horiguchi et al.), "A Flexible Redundancy Technique for High-Density DRAM's".

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