Column read amplifier power-gating technique for integrated...

Details Column read amplifier power-gating technique for integrated... Column read amplifier power-gating technique for integrated...

2006-01-24

2006-01-24

Phan, Trong (Department: 2827)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S207000, C365S208000

Reexamination Certificate

active

06990029

ABSTRACT:
A column read amplifier power-gating technique for DRAM devices and those devices incorporating embedded DRAM which incorporate a power-down (or Sleep) mode of operation which overcomes the deficiencies of conventional power-gating approaches by eliminating the need for a large, separate power-gating transistor thereby saving on-chip area yet still reducing power during Sleep Mode. In operation, the column select signal YR is controlled such that it is driven below VSS during Sleep Mode when N-channel pass transistors are used in the column read amplifier or to a supply voltage level of VCC when P-channel devices are used instead. This significantly reduces the current through the pass transistors and yet causes no reduction in the switching speed of the column read amplifiers.

REFERENCES:
patent: 6208575 (2001-03-01), Proebsting
patent: 6275432 (2001-08-01), Hardee
patent: 6449182 (2002-09-01), Ooishi
Min, Kyeong-Sik, Kawaguchi, Hiroshi, Sakurai, Takayasu, ZigZag Super Cut-off CMOS (ZSCCMOS) Block Activation with Self-Adaptive Voltage Level Controller: An Alternative to Clock-Gating Scheme in Leakage Dominant Era, 2003 IEEE International Solid-State Circuits Conference, Feb. 12, 2003,Salon 1-6, pp. 400-401 and 501-502.

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