Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
1996-07-29
2002-05-28
Paladini, Albert W. (Department: 2827)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S260000, C361S760000, C361S773000, C361S779000
Reexamination Certificate
active
06395991
ABSTRACT:
FIELD OF THE INVENTION
The present invention is directed to column array connections attaching modules or chips, generally substrates, with low coefficients of thermal expansion to printed circuit boards having materially higher coefficients of thermal expansion. More particularly, the present invention is directed to structural refinements suitable to reinforce the substrates for applications requiring heat sinks or the like.
BACKGROUND OF THE INVENTION
Integrated circuit packages and their applications have undergone tremendous change in evolving to what is presently considered a contemporary design. Integrated circuit die (chip) sizes having increased dramatically, as have their operational clock rates. At the same time both the active and passive integrated circuit device dimensions have decreases. The circuit functions available from each integrated circuit die are now materially greater. As a consequence of such trends, integrated circuit packages require greater pin-out counts and higher power dissipation capabilities.
Numerous of the performance objectives were satisfied with ball grid array technology, including both the flip-chip and ceramic package variants. The power dissipation problem was addressed through the use of miniature heat sinks which attach directly to the flip-chip or ceramic package.
Simulation and testing of ball grid array type solder attachments involving silicon die or ceramic packages and underlying FR
4
or the like fiberglass printed circuit boards has uncovered a susceptibility to stress failures. The failures occur with thermal cycling and are attributable to the materially different coefficients of thermal expansion. The stresses experienced by the ball grid array solder connections are aggravated with package size and with forces introduced by bonded or compressively affixed heat sinks. Moreover, the number of thermal stress cycles, and associated fatigue failure rates, have increased materially with the introduction of die power management techniques which frequently cycle the die between sleep and full operation modes.
A very new connection technology capable of managing the strain caused by the mismatch in coefficients of thermal expansion involves the use of solder columns, rather than solder balls, to define the electrical connections between the ceramic or die and the printed circuit board. Typical columns have an aspect ratio of approximately 9:2 and a nominal diameter of 0.020 inches. The solder columns are formed from high melting temperature solder using a nominal 90/10 alloy of lead to tin. The columns are first bonded to the ceramic or die, and thereafter attached to the printed circuit board using conventional low melting temperature solder paste reflow techniques.
As the power dissipation of flip-chip and ceramic packaged integrated circuits have increased, now often exceeding 50 watts, the heat sink has become critical necessity. Whether the heat sink is attached to the substrate by mechanical clamping, or by bonding, or the combination, the shock, vibration and pressure effects of heavy heat sinks are more than column array solder connections alone can support.
One approach to reinforcing the solder column connections of ceramic package substrates involves the placement of kovar or cu-sil pins in the corners of the ceramic packages to maintain the position of the ceramic package in relation to the printed circuit board in the presence of the heat sink vibrations and compressive forces. Such pins are attached to the ceramic substrate by brazing. The pins are then positioned into holes in the printed circuit board. Unfortunately, the use of such pins results in numerous additional and unique manufacturing steps. Furthermore, their use is effectively limited to ceramic packages, not for flip-chip die attachments.
In view of the foregoing, there exists a need for both structures and methods by which integrated circuits, whether in flip chip die or ceramic packages, can be attached through a solder column grid array adequately to support a heat sink.
SUMMARY OF THE INVENTION
The present invention is practiced in the context of a system for connecting a substrate having a low coefficient of thermal expansion to a printed circuit board having a materially higher coefficient of thermal expansion using an array of solder columns and reflow bonding. In that context, the invention supports the substrate to permit effective heat sink contact with a structural element of the substrate, comprising an array of high melting temperature solder columns of first cross-sectional area attached to an array of electrically transmitting pads on the substrate, a set of high melting temperature solder columns of second cross-sectional area, the second cross-sectional area exceeding the first by a factor of 5 or greater, attached to pads at perimeter locations of the substrate, a plurality of connections between first and second cross-sectional area solder columns and respective pads on the printed circuit board using reflowed low temperature solder, and a heat sink thermally contacting a structural element of the substrate on a side opposite the solder column attachments.
In another form, the invention is directed to a process practiced in the context of a system for connecting a substrate having a low coefficient of thermal expansion to a printed circuit board having a materially higher coefficient of thermal expansion using an array of solder columns and reflow bonding, the method providing supports for the substrate to permit effective heat sink contact with a structural element of the substrate, comprising the steps of attaching an array of high melting temperature solder columns of first cross-sectional area to an array of electrically transmitting pads on the substrate, attaching a set of high melting temperature solder columns of second cross-sectional area, the second cross-sectional area exceeding the first by a factor of five or greater, to pads at perimeter locations of the substrate, reflowing low temperature solder to connect first and second cross-sectional area solder columns to respective pads on the printed circuit board, and connecting by thermal contact a heat sink to a structural element of the substrate on the side opposite the solder column attachments.
In a particularized form, the invention extends and refines the basic practice of using an array of solder columns to attach a substrate, whether that substrate is an integrated circuit die directly or a die mounted within a ceramic package, to a printed circuit board employing solder paste and conventional reflow techniques. Relatively lower aspect ratio solder columns are formed in the corners or other peripheral regions of the substrate, in conjunction with the formation of the thin solder column electrical interconnect array, using corresponding high melting temperature solder. The conventional and reinforcing columns are bonded to the substrate simultaneously using either a wire column attachment process or a cast column attachment process.
The substrate and attached columns are aligned with the pads on the printed circuit board using conventional fixtures. Likewise, bonding of the substrate to the printed circuit board as to both the reinforcing columns and conventional electrical signal column array is accomplished by reflowing solder paste deposited on the printed circuit board pads. Once the substrate is bonded to the printed circuit board, the reinforcing columns support the substrate and any attached heat sink. The reinforcing solder columns maintain spacing and structural integrity in presence of vibration and temperature variations.
These and other features of the invention will be more clearly understood and appreciated upon considering the detailed embodiments described hereinafter.
REFERENCES:
patent: 3871015 (1975-03-01), Lin et al.
patent: 3932934 (1976-01-01), Lynch et al.
patent: 4413308 (1983-11-01), Brown
patent: 4509096 (1985-04-01), Baldwin et al.
patent: 4561011 (1985-12-01), Kohara et al.
patent: 4604644 (1986-08-01), Beckham et al.
patent: 4664309 (1
Dockerty Robert Charles
Fraga Ronald Maurice
Ramirez Ciro Neal
Ray Sudipta Kumar
Robbins Gordon Jay
International Business Machines - Corporation
Paladini Albert W.
Salys Casimer K.
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