Column grid array for semiconductor packaging and method

Details Column grid array for semiconductor packaging and method Column grid array for semiconductor packaging and method

1997-10-31

1999-11-23

Niebling, John F.

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

438667, H01L 2144, H01L 2148, H01L 2150

Patent

active

059899352

ABSTRACT:
A method for manufacturing a column grid array semiconductor package (10, 210) may include the steps of providing a substrate material (14, 114, 214) having a first side (16, 116) and a second side (18), forming a plurality of holes (36, 136, 236) in the substrate (14, 114, 214), forming contacts (24, 124,) on the first surface (16, 116) of the substrate (14, 114, 214), filling the plurality of holes (36, 136, 236) with a conductive material (32, 132, 232) to an extent that an extension portion (28, 128, 228) is formed on the second side (18) of the substrate (14, 114, 214) to which an electrical contact may be made. The extension portion (28, 128, 228) may be coated with a capping material (40, 140, 240). The holes (36, 136, 236) may be filled with the conductive material (32, 132, 232) by placing a material (146, 246) over the hole (36, 136, 236) on the first side (16, 116) of the substrate (14, 114, 214) and filling the holes (36, 136, 236) with the conductive material (32, 132, 232). The resist (146, 246) may then be removed.

REFERENCES:
patent: 5260169 (1993-11-01), Nakano
patent: 5355283 (1994-10-01), Marrs et al.
patent: 5822856 (1998-10-01), Bhatt et al.

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