Column address decoder for two bit prefetch of semiconductor mem

Details Column address decoder for two bit prefetch of semiconductor mem Column address decoder for two bit prefetch of semiconductor mem

1999-09-30

2000-11-28

Phan, Trong

Static information storage and retrieval

Addressing

Sync/clocking

36523006, 365200, G11C 800, G11C 700

Patent

active

061544167

ABSTRACT:
A column address decoder for two bit prefetch of a semiconductor device and a decoding method thereof are provided. The column address decoder includes a memory cell array having a plurality of memory cells for storing data and redundancy memory cells for replacing poor memory cells, a plurality of bit lines connected to the memory cells, a plurality of input and output lines, a plurality of switching means connected between the bit lines and the input and output lines. It also includes an even predecoder for receiving the less significant bits of the address received as input from the outside and predecoding the less significant bits in which the least significant bit is `0` of the less significant bits, an inverting decoder for reproducing the less significant bits of the external address corresponding to the address predecoded by the even predecoder, and a redundancy enable signal generating portion for generating a redundancy enable signal for receiving the output of the inverting decoder and activating one of the redundancy memory cells. According to the present invention, the data processing speed of the semiconductor memory device is increased.

REFERENCES:
patent: Re36089 (1999-02-01), Ooishi et al.
patent: 5255228 (1993-10-01), Hatta et al.
patent: 5282173 (1994-01-01), Miyaji et al.
patent: 5315548 (1994-05-01), Ooishi et al.
patent: 5594704 (1997-01-01), Konishi et al.
patent: 5781493 (1998-07-01), Kobayashi
patent: 5798978 (1998-08-01), Yoo et al.
patent: 5815460 (1998-09-01), Watanabe
patent: 5815462 (1998-09-01), Konishi et al.
patent: 5822268 (1998-10-01), Kirihata
patent: 5870347 (1999-02-01), Keeth et al.
patent: 5880995 (1999-03-01), Kobatake
patent: 5896342 (1999-04-01), Nakao
patent: 5896345 (1999-04-01), Sohn
patent: 5901105 (1999-05-01), Ong et al.
patent: 6026036 (2000-02-01), Sekiya et al.
patent: 6064625 (2000-05-01), Tomita
Steven A. Przybylski, New DRAM Technologies, pp. 219-222, 1996.
U.S. application No. 09/170,940, Hwang, Oct. 13, 1998.

Affiliated with

Also associated with

Rating

Column address decoder for two bit prefetch of semiconductor mem does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Column address decoder for two bit prefetch of semiconductor mem, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Column address decoder for two bit prefetch of semiconductor mem will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1732422