Column address counter with minus two subtractor for address com

Details Column address counter with minus two subtractor for address com Column address counter with minus two subtractor for address com

1997-12-11

2000-09-19

Bragdon, Reginald G.

Electrical computers and digital processing systems: memory

Address formation

Incrementing, decrementing, or shifting circuitry

711218, G06F 1202

Patent

active

061227188

ABSTRACT:
The present invention is a method and circuit for providing a burst address counter with a fast burst-done signal. In a preferred embodiment, a synchronous memory device includes a counter for producing a sequence of burst addresses, based on an external address. In addition, the counter drives the burst-done signal to indicate completion of the burst sequence. The counter includes a register for receiving the external address, an incrementor for advancing the external address to produce the next address of the sequence of burst addresses, a minus-two subtractor for determining a second-to-last burst address of the burst sequence, and a comparator. By utilizing the minus-two subtractor, the comparator can determine the end of the burst sequence earlier than conventional counters. This is because the minus-two subtractor determines the next-to-last address of the sequence, which allows the comparator to start asserting the burst-done signal at an earlier time.

REFERENCES:
patent: 5208782 (1993-05-01), Sakuta et al.
Motorola Technical Information Center, Motorola Memories, 32K .times.9 Bit BurstRAM Synchronous Static RAM With Burst Counter and Self-Timed Write, Rev. 7, 1991.

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