Collimated deposition of titanium onto a substantially vertical

Details Collimated deposition of titanium onto a substantially vertical Collimated deposition of titanium onto a substantially vertical

1998-04-28

2000-09-19

Nelms, David

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438592, 438655, 438664, 438680, H01L 2144

Patent

active

061211389

ABSTRACT:
An integrated circuit fabrication process and transistor is provided in which salicidation is virtually eliminated from the spacer sidewall surface. Absent salicidation on that surface, bridging effects cannot occur regardless of the anneal conditions. The spacer sidewall surfaces is made substantially perpendicular to the substrate upper surface such that when a refractory metal is subsequently deposited on the semiconductor topography, the refractory metal will not accumulate on that perpendicular surface. The spacer is deposited from a specifically designed plasma enhanced chemical vapor deposition process to maintain the spacer sidewall surfaces commensurate with the gate conductor sidewall surfaces. The refractory metal is directionally deposited so that little if any metal will form on vertical surfaces and substantially all of the metal will deposit on horizontal surfaces.

REFERENCES:
patent: 5496750 (1996-03-01), Moslehi
patent: 5736446 (1998-04-01), Wu
patent: 5739573 (1998-04-01), Kawaguchi

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