Collector layer structure for a double hetero-junction...

Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Bipolar transistor

Reexamination Certificate

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C257SE29188

Reexamination Certificate

active

07115918

ABSTRACT:
An indium phosphide based double hetero-junction bipolar transistor with an increased collector-base breakdown voltage and a reduced operational knee voltage is provided by manipulating the conductivity in the collector region. The collector is formed using layers of different conductivities, with a region of the collector relatively close to the base being unintentionally or low doped. A voltage drop across the unintentionally doped region reduces the maximum value of the electric field and the velocity of carriers injected into the collector region at the base-collector junction. The conductivity throughout the collector region may be graded such that the highest conductivity occurs near the sub-collector and lowest conductivity occurs near the base region.

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Hong Wang and Geok Ing Ng, “Investigation of the Degradation of InGaAs/InP Double HBTs Under Reverse Base-Collector Bias Stress,” vol. 48, No. 11, IEEE Transactions on Electron Devices, pp. 2647-2654, Nov. 2001.
Hin-Fai Chau, Dimitris Pavlidis, Juntao Hu, and Kazutaka Tomizawa, “Breakdown-Speed Considerations in InP/InGaAs Single- and Double-Heterostructure Bipolar Transistors,” vol. 40, No. 1, IEEE Transactions on Electron Devices, pp. 2-8, Jan. 1993.
Peter M. Asbeck, Frank Mau-Chung Chang, Keh-Chung Wang, Gerard J. Sullivan, and Derek T. Cheung, “GaAs-Based Heterojunction Bipolar Transistors for Very High Performance Electronic Circuits,” vol. 81, No. 12, Proceedings of the IEEE, pp. 1709-1726, Dec. 1993.

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