Semiconductor device manufacturing: process – Making passive device – Trench capacitor
Reexamination Certificate
2000-06-23
2002-04-23
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making passive device
Trench capacitor
C257S301000, C257S302000, C257S303000, C438S234000
Reexamination Certificate
active
06376324
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention is directed to deep trench storage capacitors, and, more particularly, to dynamic random access memory cells in semiconductor devices.
Semiconductor devices, and memory devices in particular, typically employ capacitors for charge storage purposes. Many memory devices, such as dynamic random access memory (DRAM) cells, utilize capacitors wherein a bit of data is represented by a charge stored in the capacitor structure. Typically a DRAM cell comprises a transistor coupled to a capacitor. Referring to
FIG. 23
, the transistor includes two diffusion regions separated by a channel, above which is located a gate conductor (GC). One type of capacitor commonly employed in DRAM cells is the deep trench (DT) capacitor. A DT capacitor is a three dimensional structure formed in a silicon substrate. Typically a deep trench is formed in the silicon substrate using a conventional technique such as reactive ion etching (RIE). The trench is typically filled with n-type doped polysilicon which serves as one plate of the capacitor, usually referred to as the “storage node”. The second plate of the capacitor, usually referred to as the “buried plate”, is typically formed by outdiffusion of an n-type doped region surrounding the lower portion of the trench. A node dielectric layer is provided to separate the buried plate and the storage node thereby forming the capacitor. A node diffusion region, also referred to as the node junction, couples the capacitor to the transistor. The node junction is formed from the outdiffusion of dopants from the doped polysilicon into the silicon substrate through a buried strap provided above the doped polysilicon and connecting the doped polysilicon to the silicon substrate. Applying an appropriate voltage to the GC allows current to flow through the channel between the diffusion regions to form a connection between the capacitor and the bitline. Typically a dielectric collar is formed at an upper portion of the trench to prevent leakage of the node diffusion region to the buried plate which would degrade the retention time of the cell. A shallow trench isolation (STI) is provided in a top portion of the trench to isolate the DRAM cell from other cells in the device.
As minimum feature size and cell architecture are scaled down, robust design points for DRAM cells utilizing planar metal oxide semiconductor field effect transistors (MOSFETs) and DT capacitors are increasingly difficult to achieve. Scalability of the planar MOSFET in the environment is severely limited by gate conductor to deep trench (GC-DT) overlay tolerance and buried strap outdiffusion. One manifestation of the scalability difficulties of planar DRAM MOSFETs is degradation of the retention time, due to increased node junction leakage resulting from the very high channel doping concentrations required to suppress short-channel effects. This is particularly true for designs currently being considered for the 0.15 &mgr;m generation. The viability of such DT cell designs having planar MOSFETs will be enhanced by reducing the encroachment of the strap diffusion upon the array MOSFET. Even a reduction of 10 nm would be significant.
With presently practiced DT collar processes, a local oxidation of silicon (LOCOS) collar is employed. The uses of an oxidized, rather than deposited, collar facilitates the filling of the trench and provides increased storage capacitance. However, due to the oxidation process a portion of the DT sidewall silicon is converted to SiO2. When the strap opening is formed, part of the collar is removed to provide a path for the outdiffusion of dopant from the DT polysilicon into the silicon substrate. Therefore the initial interface for the strap diffusion is moved closer to the array MOSFET by an amount which is equal to the amount of DT sidewall silicon consumed by the collar oxidation. In other words, the distance between the GC and the DT is reduced to less than its design nominal. For a 30 nm thick collar this additional DT edge bias amounts to approximately 12 nm/edge. The additional 12 nm of DT bias/edge significantly restricts the operable process window and puts additional pressure on tightening other process controls, such as GC-DT overlay and DT critical dimension (CD) tolerance, and GC CD tolerance and bias.
There are a number of methods proposed by others for forming a deep trench capacitor which employs a dielectric collar to prevent leakage of the node junction to the buried plate.
Schrems et al. U.S. Pat. No. 5,945,704,the disclosure of which is incorporated by reference herein, discloses an improved trench capacitor having a reduced surface roughness on the trench sidewalls. By lining the lower portion of the trench with an epitaxial layer of silicon, the roughness of the surface on which the node dielectric is formed is reduced. The invention does not disclose a new or novel method for providing the dielectric collar.
Hsu et al. U.S. Pat. No. 5,395,786, the disclosure of which is incorporated by reference herein, discloses a simplified process for forming a trench capacitor that reduces cost and increases process latitude by forming the trench collar in a single step. This method requires expanding the trench sidewalls horizontally by means of an isotropic etch and then growing an oxide layer to form the trench collar. This method consumes, i.e., oxidizes, trench sidewall and thereby decreases GC-DT gap, a disadvantage avoided by the present invention..
Lam et al. U.S. Pat. No. 5,770,876, the disclosure of which is incorporated by reference herein, discloses a process for forming a semiconductor trench capacitor with a first level aligned buried strap. The invention does not disclose a new or novel method for providing the dielectric collar.
Choi et al. U.S. Pat. No. 5,723,889, the disclosure of which is incorporated by reference herein, discloses a trench capacitor with a transistor stacked vertically on top of the trench capacitor, thereby reducing the total surface area occupied by the device. The invention does not disclose a new or novel method for providing a dielectric collar.
Kennedy, U.S. Pat. No. 5,576,566, the disclosure of which is incorporated by reference herein, discloses a semiconductor device with a buried strap and insulation structure aligned with a trench capacitor. The invention does not disclose a new or novel method for providing the dielectric collar.
Hayden, U.S. Pat. No. 5,498,889, the disclosure of which is incorporated by reference herein, discloses the incorporation of a storage capacitor in a static random access memory (SRAM) device to increase total storage node capacitance. The preferred embodiment forms the SRAM over a transistor in a vertical stack configuration. The invention does not disclose a new or novel method for providing a dielectric collar.
Notwithstanding the prior art there remains a need to reduce the encroachment of strap diffusion upon the array MOSFET. The present inventors have proposed a new DT collar process which reduces the effective DT edge bias. The invention also allows a negative DT edge bias, i.e., a smaller DT width, to be achieved at the top of the DT, without compromising storage capacitance.
Thus, a purpose of the present invention is to have a method for providing a DT collar process which reduces the effective DT edge bias. It is another purpose of the present invention to have a method for providing a DT collar process which allows a negative DT edge bias.
These and other purposes of the present invention will become more apparent after referring to the following description considered in conjunction with the accompanying drawings.
BRIEF SUMMARY OF THE INVENTION
The present invention discloses a new DT collar process which reduces the effective DT edge bias, i.e., maximizes the GC-DT gap. A first embodiment utilizes a thin epitaxial silicon (epi) layer with minimal crystal defects suitable for allowing a negative DT edge bias, i.e., a smaller DT width, to be achieved at the top of the DT, without compromising storage capacitance. The epi lay
Divakaruni Ramachandra
Gruening Ulrike
Mandelman Jack A.
Radens Carl J.
Sudo Akira
Blecker Ira D.
Lee Dung A
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