Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2000-06-19
2002-08-06
Sherry, Michael J. (Department: 2829)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
Reexamination Certificate
active
06429092
ABSTRACT:
BACKGROUND
1. Technical Field
This disclosure relates to semiconductor fabrication and more particularly, to a method for forming an oxide collar in a deep trench by employing a selective oxide deposition.
2. Description of the Related Art
Semiconductor memory devices, for example, dynamic random access memories (DRAM=s), include capacitors to store data which are accessed by transistors (e.g., access transistors). Deep trench (DT) capacitors are among the types of capacitors employed in DRAM technology. Deep trench capacitors are typically buried within a semiconductor substrate. In the case of a p-type doped Si-substrate, a bottom portion of the trenches has to be n-type doped to form a buried plate (e.g., one electrode of the capacitor). This buried plate is separated from the n-type doped source region of the access transistor by a p-type doped substrate region. Consequently, there is an n/p
junction along the vertical side of the DT.
The n/p
junction forms a transistor by itself. This undesired transistor is called a vertical device or a parasitic device and may cause a severe leakage of charge from the buried plate to the access transistor if it is turned on. To prevent this vertical leakage, a thick dielectric layer is formed along the n/p
junction. This dielectric layer is called the trench collar and conventionally includes SiO
2
. This oxide collar has the same function as a gate oxide of the access transistor. The thickness of the collar oxide determines the threshold voltage V
t
of the parasitic device. Once the applied voltage is larger than V
t
, the transistor is turned on and charge can detrimentally flow through the n/p
junction. This should be avoided in the vertical device, i.e. the oxide collar thickness must be large enough that the vertical device never turns on during DRAM operation.
Conventionally voltages in the order of V
D
/2 are applied to the DT where V
D
is the power supply voltage (typically, about 3 V). To prevent the vertical device from turning on a collar oxide thickness above about 25 nm is needed. Currently this collar oxide is formed by a chemical vapor deposition (CVD) or a physical vapor deposition (PVD) with a subsequent collar open etch. Alternately, a LOCOS process (localized oxidation of silicon) may be employed. The LOCOS process permits for an easier (cheaper) process integration flow if compared to the PVD/CVD processes and is more suitable for smaller ground rules (for a better trench profile). However, the conventional LOCOS collar has the following drawbacks:
1) The LOCOS oxide thickness shows a severe dependence on the Si-crystal orientation of the semiconductor substrate resulting in a non-uniform collar with thin regions. In the thin regions V
t
drops significantly causing reliability problems.
2) The trench opening (CD) for the LOCOS collar has to be reduced as the collar oxidation consumes silicon of the substrate.
3) To prevent oxidation of the trench sidewalls a nitride liner is needed in the bottom part of the trench where no oxide is to be formed. In case of the conventional LOCOS process, this liner has to be thicker than 5 or 6 nm to prevent oxidation of the Si interface. This thick layer is difficult to remove.
Therefore, a need exists for methods, which overcome the disadvantages of the prior art. A further need exists for a selective deposition process, which forms an oxide collar selectively on silicon.
SUMMARY OF THE INVENTION
A method for forming an oxide collar in a trench, in accordance with the present invention, includes forming a trench in a silicon substrate, and depositing and recessing a nitride liner in the trench to expose a portion of the silicon substrate on sidewalls of the trench. An oxide is deposited selective to the nitride liner on the portion of the silicon substrate. Residue oxide is removed from surfaces of the nitride liner to form a collar in the trench.
In other methods, the step of depositing an oxide selective to the nitride liner on the portion of the silicon substrate may include the step of depositing an ozone activated tetraethyl orthosilicate (TEOS) oxide selective to the nitride liner on the portion of the silicon substrate. The step of depositing an ozone activated tetraethyl orthosilicate (TEOS) oxide selective to the nitride liner on the portion of the silicon substrate may include the step of providing an initial gas flow ratio of TEOS to ozone of approximately 10 and attaining a steady-state gas flow ratio of TEOS to ozone of 0.4. The step of etching residue oxide from surfaces of the nitride liner to form a collar in the trench may include the step of wet etching the residue oxide. The step of depositing and recessing a nitride liner may include the steps of filling the trench with a resist over the nitride liner, recessing the resist to expose a portion of the nitride liner and etching the nitride liner to a top level of the resist in the trench to expose the portion of the substrate in the trench. The nitride liner may be between about 2 nm and 3 nm in thickness. The method further includes the step of forming a buried plate adjacent to a lower portion of the trench. The method may include the step of annealing the oxide.
A method for forming an oxide collar in a trench, in accordance with the present invention, includes the steps of forming a trench in a silicon substrate, depositing a nitride liner in the trench, and recessing the nitride liner to expose a portion of the silicon substrate on sidewalls of the trench. An ozone activated tetraethyl orthosilicate (TEOS) oxide is deposited selective to the nitride liner on the portion of the silicon substrate. The oxide is substantially homogenous in thickness such that the thickness of the oxide is independent of a crystallographic orientation of the portion of the substrate on which the oxide is formed. Residue oxide is etched from surfaces of the nitride liner to form a collar in the trench.
The step of depositing an ozone activated tetraethyl orthosilicate (TEOS) oxide may include the step of providing an initial gas flow ratio of TEOS to ozone of approximately 10 and attaining a steady-state gas flow ratio of TEOS to ozone of 0.4. The step of etching residue oxide from surfaces of the nitride liner to form a collar in the trench may include the step of wet etching the residue oxide. The step of recessing a nitride liner may include the steps of filling the trench with a resist over the nitride liner, recessing the resist to expose a portion of the nitride liner and etching the nitride liner to a top level of the resist in the trench to expose the portion of the substrate in the trench. The nitride liner may be between about 2 nm and 3 nm in thickness. The method may include the step of forming a buried plate adjacent to a lower portion of the trench. The method may further include the step of annealing the oxide.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
REFERENCES:
patent: 5399389 (1995-03-01), Hieber et al.
patent: 5416041 (1995-05-01), Schwalke
patent: 5656535 (1997-08-01), Ho et al.
patent: 5763315 (1998-06-01), Benedict et al.
patent: 5965203 (1999-10-01), Gabric et al.
Elbel et al., “A New STI Process Based on Selective Oxide Deposition,” IEEE, Symposium on VLSI Technology Digest of Technical Papers, 1998, pp. 208-209.
Beintner Jochen
Gabric Zvonimir
Gruening Ulrike
Michaelis Alexander
Spindler Oswald
Braden Stanton
Infineon - Technologies AG
Kilday Lisa
Sherry Michael J.
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