Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Patent
1996-01-23
1998-02-24
Westin, Edward P.
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
375257, H03K 1716
Patent
active
057214972
ABSTRACT:
Cold termination is provided at the bus output port of a last device coupled to a bus. Each device includes a termination integrated circuit ("TIC") that receives operating voltage from bus-provided V.sub.TERM potential. The TIC includes a series-coupled resistor-capacitor ("R-C") connected between V.sub.TERM and ground. The "R-C" junction defines a SENSE node that is coupled to a groundable pin on the device bus output port and to a SENSE input node on the TIC. If a bus cable connector is attached to the device bus output port, attachment grounds the groundable pin, and thus the TIC SENSE node is "0", which disables TLC bus termination. But if no connector is attached, the groundable pin floats to a potential approximating V.sub.TERM, and is a logical "1", which enables TIC bus termination. Preferably an inverter is series-coupled between the TIC SENSE node and input SENSE node to accommodate a TIC that enables termination with a "0" input SENSE signal. A visual indicator coupled between V.sub.TERM and the inverter output illuminates when TIC bus termination is enabled. The present invention can cold terminate a wide-bus at a device, permitting the bus to propagate downstream as a narrow bus, and then cold terminate the narrow bus at the bus output port of a last device coupled to the bus.
REFERENCES:
patent: 5313595 (1994-05-01), Lewis et al.
patent: 5434516 (1995-07-01), Kosco
patent: 5513373 (1996-04-01), Damkier
patent: 5568046 (1996-10-01), Samela et al.
patent: 5583448 (1996-12-01), Corder et al.
Roseen Richard
Sun Microsystems Inc.
Westin Edward P.
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