Cold clock power reduction

Details Cold clock power reduction Cold clock power reduction

2006-05-23

2006-05-23

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07051294

ABSTRACT:
A multi-mode latch timing circuit has a first set of latches and a second set of latches in each logical path. In a first mode of operation, first and second phase clock signals are provided so that the latch timing circuit functions as a two-phase non-overlapping transparent latch timing circuit. In a second mode of operation, the first set of latches is held in a transparent state in some or all of the logical paths, thereby reducing clock power. In one embodiment, the first set of latches in each long path is held in a transparent state while the second phase clock signal is supplied to the second set of latches. In one embodiment, the first set of latches in each short path is held in a transparent state while a second phase clock signal comprised of shortened duty cycle pulses is supplied to the second set of latches.

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