Coherent variable length reads which implicates multiple cache l

Details Coherent variable length reads which implicates multiple cache l Coherent variable length reads which implicates multiple cache l

1998-01-26

2000-05-09

Yoo, Do Hyun

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711169, 710107, 710128, G06F 1206, G06F 1316

Patent

active

060617640

ABSTRACT:
Method and apparatus for processing serial bus read requests in a memory controller when the memory controller interfaces to both a pipelined bus and a serial bus. According to the method, the read request message is received and is split into several atomic transactions. The atomic transactions are issued on the pipelined bus. Data related to the several atomic transactions is stored in a queue. The requested data is read from the queue and placed in a response message on the serial bus.

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