Coherent variable length reads from system memory

Details Coherent variable length reads from system memory Coherent variable length reads from system memory

2000-05-08

2001-10-02

Nguyen, Hiep T. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

C711S141000, C710S120000

Reexamination Certificate

active

06298420

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a control protocol in memory controller that handles read requests for data of variable length from a serial bus.
Modern computer systems are multiple agent systems. An agent typically is a computer device having some processing power that performs a predetermined function of the computer system. For example, one or more processors may perform operations of a computer program. A memory controller administers the reading and writing of program instructions ani data from memory to other agents. Input-output (I/O) devices communicate data to and from the computer system to its external environment.
The agents must coordinate with one another to perform their respective functions. Accordingly, the agents communicate with one over a bus according to a predetermined bus protocol. As various agents have evolved, varying bus protocols have become known. Bus protocols typically are not compatible with other bus protocols. Each may provide different advantages or disadvantages relative to others. In a single computer system, multiple buses may be used.
FIG. 1
illustrates a multiple agent system using several buses. Agents
10
-
50
coordinate among each other via a pipelined bus
60
. Agent
50
may be a memory and input/output controller
100
(“MIOC”) and include a memory subsystem
200
. The MIOC cooperates with other agents to exchange data between the memory
200
and data caches of the agents, such as cache
14
. The MIOC
100
interfaces the agents on the pipelined bus
60
to agents of one or more secondary, serial buses
70
. The serial bus
70
interfaces the MIOC
100
with other agents
80
. The serial bus agents
80
may be bridging agents that interface the serial bus
70
tertiary buses
90
. Thus, a single computer system may include a variety of buses each operating according to its own protocol.
A “transaction” is a set of activities on a bus related to a single request issued by an agent. In a pipelined bus, a transaction proceeds sequentially through several phases. Signaling for each phase may be exchanged among the agents
10
-
50
on different data lines (not shown) contained within the pipelined bus
60
. Consequently, at any given time, several transactions may be in progress simultaneously on the pipelined bus provided that they are in mutually different phases. Transactions on the pipelined bus are processed in the order in which they are posted.
As a representative example, the known Pentiumr Pro processor, supports a pipelined bus that advances a transaction through six phases:
Arbitration, in which an agent becomes the bus owner,
Request, in which a request is made identifying an address,
Error, in which errors in the request phase are identified,
Snoop, in which cache coherency checks are made,
Response, in which the failure or success of the transaction is indicated, and
Data, in which data may be transferred.
In the Pentium® Pro processor, up to four cycles of 8 byte data may be transferred in the data phase. Not all phases occur for every transaction. Other processors support pipelined buses in other ways.
In a serial bus
70
, messages are exchanged among agents to implement a transaction. A first message carries a request from one agent to another. A second message carries a response to the request back to the requesting agent. Several transactions may be underway at once on the serial bus. Messages include a transaction ID field to identify the transaction to which the message relates.
On the serial bus, read request messages identify the request type. The message also includes an address of data to which the request is directed and a length of data to be read. The address identifies a starting point for reading data; the length field indicates how much data should be read from memory beginning at that address.
Read requests typically are answered by a response that provides the requested data. The response message typically includes a header that includes a response type, a transaction ID and a length field identifying the length of the data that follows. When the read request cannot be fulfilled for any reason, the request may be answered by a RETRY response.
The length of data that may be transferred in a transaction on the serial bus
70
is not limited in the same way that transactions on the pipelined bus
60
are limited. For example, data of several cache lines may be transferred in a single response on the serial bus
70
. However, when data of a transaction is transferred on the serial bus
70
, all the data must be transferred in a single response that completes the transaction. The data may not be split into two responses.
To simplify terminology herein, transactions performed on the pipelined bus
60
are referred to as “pipelined bus transactions.” Transactions performed on the serial bus
70
are referred to as “serial bus transactions.”
As is known, data is stored in memory
200
organized as cache lines. The size of a cache line typically relates to the largest increment of data that may be transferred in a single pipelined bus transaction. For example, in the Pentium® Pro, a cache line is 32 bytes long (4 cycles of 8 byte data). The cache line is broken up into an integral number of “cache segments.” Cache segments are a basic increment of data that is transferred in a single cycle of data transfer, for example, 8 bytes in the Pentium® Pro processor.
In the pipelined bus
60
, if an agent requires data of multiple cache lines, the agent would issue multiple requests on the external bus. The data would be transferred to the requesting agent in accordance with the several transactions. Depending on the operations to be performed by the other agents' on the pipelined bus, the multiple requests of the first agent may or may not be performed sequentially on the pipelined bus
60
.
It is desirable for an MIOC
100
to receive and process serial bus transactions that transfer data exceeding a cache line. By doing so, throughput of the serial bus
70
is increased. However, the MIOC
100
must coordinate with agents on the pipelined bus
60
, for cache coherency and other purposes. An agent
10
may modify data at an address and store the modified data in an internal cache
14
without notifying other agents on the pipelined bus
60
. To respond to a read request from the serial bus
70
, the MIOC
100
must perform cache coherency checks to determine whether modified copies of the requested data exist. The bus protocol of the pipelined bus
60
does not recognize cache coherency transactions in excess of a cache line. No known memory controller processes read requests from a serial bus
70
that implicate data of multiple cache lines.
Further, agents of a serial bus
70
may handle data in increments that are smaller than a cache segment. No known memory controller processes read requests from a serial bus
70
that implicate data at a data segment level, where data segments are smaller than cache segments on the pipelined bus.
Accordingly, there is a need in the art for a memory controller that interfaces a pipelined bus with a serial bus that processes serial bus transactions that requests data of a variable number of data segments, the data segments being independent of the cache lines.
SUMMARY OF THE INVENTION
Embodiments of the present invention provide a method of processing serial bus read requests in a memory controller when the memory controller interfaces to both a pipelined bus and a serial bus. According to the method, the read request message is received and is split into several atomic transactions. The atomic transactions are issued on the pipelined bus. Data related to the several atomic transactions is stored in a queue. The requested data is read from the queue and placed in a response message on the serial bus.


REFERENCES:
patent: 5345566 (1994-09-01), Tanji et al.
patent: 5546546 (1996-08-01), Bell et al.
patent: 5586274 (1996-12-01), Bryg et al.
patent: 5611058 (1997-03-01), Moore et al.
patent: 5623628 (1997-04-01), Brayton et al.
patent: 5737756 (1

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