Coherent shared memory processing system

Details Coherent shared memory processing system Coherent shared memory processing system

2007-01-30

2007-01-30

Elmore, Reba I. (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S147000, C711S154000

Reexamination Certificate

active

11182123

ABSTRACT:
A shared memory system includes a plurality of processing nodes and a packetized input/output link. Each of the plurality of processing nodes includes a processing resource and memory. The packetized I/O link operably couples the plurality of processing nodes together. One of the plurality of processing nodes is operably coupled to: initiate coherent memory transactions such that another one of plurality of processing nodes has access to a home memory section of the memory of the one of the plurality of processing nodes; and facilitate transmission of a coherency transaction packet between the memory of the one of the plurality of processing nodes and the another one of the plurality of processing nodes over the packetized I/O link.

REFERENCES:
patent: 6240501 (2001-05-01), Hagersten
patent: 6944719 (2005-09-01), Rowlands et al.

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