Computer graphics processing and selective visual display system – Computer graphics display memory system – Graphic display memory controller
Reexamination Certificate
2006-06-01
2010-06-01
Tung, Kee M (Department: 2628)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Graphic display memory controller
C345S502000
Reexamination Certificate
active
07728841
ABSTRACT:
In a multiple render target mode, a pixel shader computes color values for pixels and stores the computed color values in a register file. The register file acts as a buffer for the computed color values. Conventionally writing pixels in the order they are received (pixel-major order) can result in large strides across memory in the frame buffer. At least a minimum amount of work should be done within a DRAM page, for example, to cover the overhead required in opening the DRAM page. Therefore, color values are written from the register file to two or more targets in a frame buffer in a target-major order within a segment. Writing in a target-major order (sequential with respect to targets but non-sequential with respect to quads received and processed) yields coherent writes to frame buffer memory and improves memory efficiency.
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T. Gleerup, Gleerup, T.; Holten-Lund, H.; Madsen, J.; Pedersen, S., “Memory architecture for efficient utilization of SDRAM: a case study of the computation/memory access trade-off,” Hardware/Software Codesign, 2000. Codes 2000. Proceedings of the Eighth International Workshop on , vol., no., pp. 51-55, 2000.
Molnar Steven
Nordquist Bryon
NVIDIA Corporation
Perromat Carlos
Townsend and Townsend / and Crew LLP
Tung Kee M
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