Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2011-04-19
2011-04-19
Zaman, Faisal M (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S306000, C711S141000, C711S210000
Reexamination Certificate
active
07930459
ABSTRACT:
According to some embodiments, data to be exchanged via a system input output interface may be determined at a processor. It may then be arranged to exchange the data via a coherent input output device coupled to a coherent system interconnect. Other embodiments are described.
REFERENCES:
patent: 4564900 (1986-01-01), Smitt
patent: 5371861 (1994-12-01), Keener et al.
patent: 5630163 (1997-05-01), Fung et al.
patent: 5632038 (1997-05-01), Fuller
patent: 5701483 (1997-12-01), Pun
patent: 5717663 (1998-02-01), Fujita
patent: 5717952 (1998-02-01), Christiansen et al.
patent: 6219737 (2001-04-01), Chen et al.
patent: 6314486 (2001-11-01), Schulz et al.
patent: 6314496 (2001-11-01), Razdan et al.
patent: 6353877 (2002-03-01), Duncan et al.
patent: 6389526 (2002-05-01), Keller et al.
patent: 6636926 (2003-10-01), Yasuda et al.
patent: 6636947 (2003-10-01), Neal et al.
patent: 6647453 (2003-11-01), Duncan et al.
patent: 6681283 (2004-01-01), Thekkath et al.
patent: 6721813 (2004-04-01), Owen et al.
patent: 6826653 (2004-11-01), Duncan et al.
patent: 6832268 (2004-12-01), Tan et al.
patent: 6836813 (2004-12-01), Gulick
patent: 6851009 (2005-02-01), Regula
patent: 6862646 (2005-03-01), Bonola et al.
patent: 6883047 (2005-04-01), Warren et al.
patent: 6883057 (2005-04-01), Moy
patent: 6934806 (2005-08-01), Genduso et al.
patent: 7000089 (2006-02-01), Durr et al.
patent: 7124252 (2006-10-01), Khare et al.
patent: 7206879 (2007-04-01), Sano et al.
patent: 7210000 (2007-04-01), Creta et al.
patent: 7260749 (2007-08-01), Cox
patent: 7383409 (2008-06-01), Steely et al.
patent: 7643825 (2010-01-01), Fritsch et al.
patent: 7774522 (2010-08-01), Bouvier
patent: 2002/0004886 (2002-01-01), Hagersten et al.
patent: 2004/0078682 (2004-04-01), Huang
patent: 2006/0004965 (2006-01-01), Tu et al.
patent: 2006/0123195 (2006-06-01), Mukherjee
patent: 2008/0229009 (2008-09-01), Gaither et al.
patent: 2009/0089475 (2009-04-01), Chitlur et al.
patent: 2009/0327564 (2009-12-01), Chitlur
patent: 2271202 (1994-04-01), None
patent: 2003030048 (2003-01-01), None
patent: 2010015572 (2010-01-01), None
patent: 2010027048 (2010-02-01), None
Ikedo et al., “An architecture based on the memory mapped node addressing in reconfigurable interconnection network”, Mar. 17-21, 1997, IEEE, Proceedings of the Second Aizu International Symposium on Parallel Algorithms/Architecture Synthesis, pp. 50-57.
Tomasevic et al., “Hardware approaches to cache coherence in shared-memory multiprocessors, Part 1”, Oct. 1994, IEEE, IEEE Micro, vol. 14, No. 5, pp. 52-59.
Kumar et al., “Efficient and scalable cache coherence schemes for shared memory hypercube multiprocessors”, Nov. 14-18, 1994, IEEE, Proceedings of Supercomputing '94, pp. 498-507.
Chang et al., “An efficient hybrid cache coherence protocol for shared memory multiprocessors”, Aug. 12-16, 1996, IEEE, Proceedings of the 1996 International Conference on Parallel Processing, vol. 1, pp. 172-179.
Chitlur Nagabhushan
Dunning Dave
Liu Ling
Rankin Linda
Song Chuanhua
Buckley Maschoff & Talwalkar LLC
Intel Corporation
Zaman Faisal M
LandOfFree
Coherent input output device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Coherent input output device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Coherent input output device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2734933