Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
1999-08-12
2004-01-20
Ray, Gopal C. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C711S141000
Reexamination Certificate
active
06681283
ABSTRACT:
FIELD OF THE INVENTION
This invention relates in general to the field of computer architecture, and more specifically to a data coherency mechanism for an on-chip split transaction system bus.
BACKGROUND OF THE INVENTION
A system bus in a computing system provides a communication channel between computing devices, such as microprocessors, graphics processors, direct-memory-access (DMA) controllers, and other devices such as memory, keyboard, monitor, video controllers, sound generation devices, etc. The system bus typically includes data paths for memory addresses, data, and control information. In some instances, a processor multiplexes (i.e., shares) address and data information over the same signal lines, albeit at different times. That is, a processor sends address information out over the address/data pins during a first time period and later uses the same address/data pins to send or receive data. Alternatively, many processors utilize separate signal lines for address and data information.
In operation, processors communicate with memory when they need to fetch instructions. During execution of instructions, processors might be required to read data from memory, or from another device such as an input/output (I/O) port. And, upon completion of instructions, processors might be required to write data to memory, or to another device. A typical scenario for accessing memory to obtain instructions and data is similar to the following:
1. A processor presents a memory address for an instruction on address lines of a system bus, and provides control information on control lines of the system bus to indicate that the operation is a read.
2. In response to the address and control information being placed on the system bus, memory places an instruction on data lines of the system bus, which are then read by the processor. The data is typically placed on the data lines N cycles after the address information has been placed on the address lines, where N is a positive integer and varies depending on the speed of the memory.
3. During execution of the instruction, if data is required, a memory address for the data is placed on the address lines of the system bus, and control information is placed on the control lines of the system bus to indicate a read.
4. Again, the memory places data corresponding to the memory address on the data lines of the system bus.
5. If the instruction needs to write to memory, the memory address for the write is placed on the address lines of the system bus, and control information is placed on the control lines to indicate a write.
6. N cycles after the memory address is presented, the data to be written is placed by the microprocessor on the data lines of the system bus. The memory uses the memory address presented in step
5
, and places the data on the data lines into memory at that address.
One skilled in the art will appreciate from the above that the system bus provides the necessary physical interface between a processing device, and other devices (such as memory) that are external to it. A system bus also provides the protocol necessary for communicating between devices. That is, the protocol defines when address, data, and control signals must appear on the system bus, in relation to each other. For example, in the illustration presented above, address information appears in parallel with control information. At some time later, data information is presented by the processor, or is provided by memory.
In environments where there is only one device capable of initiating bus activity (a uni-master environment), the above described sequence is generally sufficient. However, in environments where multiple processors compete for access to shared devices, arbitration is needed to assign time on the bus to the multiple processors.
For example, if there are two processors on a system bus, both competing for access to slave devices (such as memory), typical systems provide an arbitration protocol between the devices to establish which one has the right to begin. On the Pentium bus (designed by Intel Corporation), a processor requests access to the bus by asserting a “bus request” signal. If the processor receives a “grant” signal, either from another processor, or from an external arbitration device, then it begins a transaction by placing address and control information on the bus. When it receives (or writes) data on the bus, it relinquishes control of the bus to the next processor. If another processor required access to the bus during the transaction, it would have to wait until the entire transaction (including the address and data portions of the transaction) completed. In most situations, it is undesirable to deny a processor access to a bus pending completion of an entire transaction by another processor.
One solution to this problem has been to separate the address and data bus portions of the system bus, and to provide separate arbitration for gaining access to each of the buses. For example, rather than requesting access (or master) of the system bus, a first processor may request access to the address bus. If the address bus is available, the first processor can present address information on the address lines, even though a second processor is bus master of the data bus. Access to the data bus by the first processor operates in a similar fashion.
Thus, by separating arbitration for accessing the address bus from that of the data bus, multiple masters are allowed to utilize portions of the system bus simultaneously. An example of an environment that provides for such split address and data buses is the system bus for the PowerPC 603, manufactured by Motorola.
When the address and data portions of a bus are separate, and are shared by multiple bus masters, a system is required to allow master devices to request, and gain access to the address and data buses, independently. This is typically provided via an arbiter, and an arbitration protocol.
The arbiter is coupled to each device on the bus that can act as a master device. A master that wishes to access either the address or data portions of the system bus presents a bus request (address bus request, or data bus request) to the arbiter. The arbiter, upon receipt of a request, utilizes its predefined protocol to determine when to grant the master access to either of the address or data bus. When it determines that the requesting master can access the address bus or the data bus, it provides that master with a bus grant signal (pertaining to the requested bus). Upon receipt of the grant signal, the requesting master begins driving the bus (address or data).
In multi-master environments, there are typically a number of locations where data may be stored. For example, it is common for a memory, or cache, to be placed within modern microprocessors to allow them to quickly access data or instructions without requiring that the processors access the memory on the system bus. Although the size of the cache is usually small compared to the memory on the system bus, every time a processor reads or writes data to a memory location that is already in its cache, activity on the system bus is reduced, or temporarily eliminated. An example of this is provided below using the split transaction bus described above.
1. If the data at address 1FFFH (where “H” stands for hexadecimal) is not in the cache, the master requests access to the address bus.
2. The arbiter grants the master access to the address bus.
3. The master asserts a read command, and places the address 1FFFH on the address bus.
4. When the memory controller is ready to respond to the read, it requests access to the data bus.
5. The arbiter grants the memory controller access to the data bus.
6. The memory controller places the data at address 1FFFH on the data bus.
7. The master receives the data.
If the data at memory address 1FFFH were already in the processor's cache, none of the above steps would have been necessary. Rather, the processor would have simply retrieved the data from its cache, without initiating any activity on the syste
Thekkath Radhika
Uhler G. Michael
Huffman James W.
MIPS Technologies Inc.
Ray Gopal C.
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