Coherency management for a “switchless”...

Details Coherency management for a “switchless”... Coherency management for a “switchless”...

2006-09-19

2006-09-19

Padmanabhan, Mano (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

Reexamination Certificate

active

07111130

ABSTRACT:
A shared memory symmetrical processing system including a plurality of nodes each having a system control element for routing internodal communications. A first ring and a second ring interconnect the plurality of nodes, wherein data in said first ring flows in opposite directions with respect to said second ring. A receiver receives a plurality of incoming messages via the first or second ring and merges a plurality of incoming message responses with a local outgoing message response to provide a merged response. Each of the plurality of nodes includes any combination of the following: at least one processor, cache memory, a plurality of I/O adapters, and main memory. The system control element includes a plurality of controllers for maintaining coherency in the system.

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